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| BT8960 Single-Chip 2B1Q Transceiver The BT8960 is a full-duplex 2B1Q transceiver based on Rockwell's HDSL technology. It supports Nx64 kbps transmission of more than 18,000 feet over 26 AWG copper telephone wire without repeaters. Small size and low power dissipation make the BT8960 ideal for line-powered voice pairgain systems capable of providing four or six clear 64 kbps channels. The BT8960 is a highly integrated device that includes all of the active circuitry needed for a complete 2B1Q transceiver. In the receive portion of the BT8960, a variable gain amplifier optimizes the signal level according to the dynamic range of the analog-to-digital converter. Once the signal is digitized, sophisticated adaptive echo cancellation, equalization, and detection DSP algorithms reproduce the originally transmitted far-end signal. In the transmitter, the transmit source and scrambler operation is programmable via the microcomputer interface. A highly linear digital-to-analog converter with programmable gain, sets the transmission power for optimal performance. A pulse-shaping filter and a low distortion line driver generate the signal characteristics needed to drive a large range of subscriber lines at low-bit error rates. Startup and performance monitoring operations are controlled via the microprocessor interface. C-language source code supporting these operations is supplied under a no-fee license agreement from Rockwell. The BT8960 includes a glueless interface to both Intel and Motorola microprocessors. Distinguishing Features * * Single-chip 2B1Q transceiver solution All 2B1Q transceiver functions integrated into a single monolithic device - Receiver gain control and A/D converter - DSP functions including echo cancellation, equalization, timing recovery, and symbol detection - Programmable gain transmit DAC, pulse-shaping filter and line driver Supports operation from 160 to 416 kbps Capable of transceiving over the ANSI T1.601 and ETSI ETR 080 ISDN test loops Flexible Monitoring and Control - Glueless interface to Intel 8051 and Motorola 68302 processors - Access to embedded filters, performance meters and timers Backwards compatible with Bt8952 software API commands JTAG/IEEE Std 1149.1-1990 compliant Single +5 V power supply operation 600 mW power consumption at 288 kbps (typical) 100-pin PQFP package -40C to +85C operation * * * * Functional Block Diagram * * Analog Receive Variable Gain Amplifier Analogto-Digital Converter Digital Signal Processor Recovered Data and Clock * * * MPU Bus Microcomputer Interface Programmable Gain DAC Framer/ Channel Unit Interface Applications Transmit Data Analog Transmit Line Driver PulseShaping Filter * * * * * * * Voice/data pairgain systems Internet connectivity ISDN basic-rate interface concentrators ISDN H0 transport Extended range fractional T1/E1 Cellular/microcellular base stations Personal Communications Systems (PCS) radio ports and cell switches Ordering Information Order Number BT8960EPF Package 100-Pin Plastic Quad Flat Pack (PQFP) Ambient Temperature -40C to +85C Copyright (c) 1997 Rockwell Semiconductor Systems, Inc. All rights reserved. Print date: December 1997 Rockwell Semiconductor Systems, Inc. reserves the right to make changes to its products or specifications to improve performance, reliability, or manufacturability. Information furnished is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by its implication or otherwise under any patent or intellectual property rights of Rockwell Semiconductor Systems, Inc. Rockwell Semiconductor Systems, Inc. products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a Rockwell Semiconductor Systems, Inc. product can reasonably be expected to result in personal injury or death. Rockwell Semiconductor Systems, Inc. customers using or selling Rockwell Semiconductor Systems, Inc. products for use in such applications do so at their own risk and agree to fully indemnify Rockwell Semiconductor Systems, Inc. for any damages resulting from such improper use or sale. Bt is a registered trademark of Rockwell Semiconductor Systems, Inc. SLC(R) is a registered trademark of AT&T Technologies, Inc. Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders. Specifications are subject to change without notice. PRINTED IN THE UNITED STATES OF AMERICA Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix 1.0 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Functional Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.1 Transmit Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.2 Receive Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.3 Timing Recovery and Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.4 Microcomputer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.5 Test and Diagnostic Interface (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 4 4 1.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.1 Voice/Data Pairgain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.2 Internet Connectivity Transport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2.3 ISDN Basic Rate Interface Concentrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 Transmit Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.1 Symbol Source Selector/Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 Variable Gain Digital-to-Analog Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.3 Pulse-Shaping Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.4 Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Variable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Analog-to-Digital Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Digital Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.1 Digital Front-End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.2 Offset Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.3 DC Level Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.4 Signal Level Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.5 Overflow Detection and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.6 Far-End Level Meter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.7 Far-End Level Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . N8960DSB 16 18 18 18 19 20 20 21 22 22 22 22 22 22 2.2 Receive Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 iii Table of Contents BT8960 Single-Chip 2B1Q Transceiver 2.2.4 Echo Canceler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4.1 Linear Echo Canceler (LEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4.2 Nonlinear Echo Canceler (NEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5 Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5.1 Digital Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5.2 Feed Forward Equalizer (FFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5.3 Error Predictor (EP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5.4 Decision Feedback Equalizer (DFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5.5 Microcoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.6 Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.6.1 Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.6.2 Peak Detector (PKD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.6.3 Error Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.6.4 Scrambler Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.6.5 Sync Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.6.6 Detector Meters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 23 23 23 23 24 24 24 24 24 24 25 25 25 26 26 2.3 Timing Recovery and Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.0.7 Timing Recovery Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3.0.8 Crystal Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4 Channel Unit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.5 Microcomputer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.5.1 Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 Microcomputer Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2.1 RAM Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2.2 Multiplexed Address/Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2.3 Separated Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.3 Interrupt Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.4 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.5 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.6 Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 32 33 33 33 33 34 34 34 2.6 Test and Diagnostic Interface (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.1 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.2.1 0x00--Global Modes and Status Register (global_modes) . . . . . . . . . . . . . . . . . . 3.2.2 0x01--Serial Monitor Source Select Register (serial_monitor_source) . . . . . . . . . 3.2.3 0x02--Interrupt Mask Register Low (mask_low_reg) . . . . . . . . . . . . . . . . . . . . . . 3.2.4 0x03--Interrupt Mask Register High (mask_high_reg) . . . . . . . . . . . . . . . . . . . . . 3.2.5 0x04--Timer Source Register (timer_source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6 0x05--IRQ Source Register (irq_source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.7 0x06--Channel Unit Interface Modes Register (cu_interface_modes) . . . . . . . . . . 3.2.8 0x07--Receive Phase Select Register (receive_phase_select) . . . . . . . . . . . . . . . . 3.2.9 0x08--Linear Echo Canceller Modes Register (linear_ec_modes) . . . . . . . . . . . . . 44 44 45 46 46 47 47 48 48 iv N8960DSB BT8960 Single-Chip 2B1Q Transceiver Table of Contents 3.2.10 0x09--Nonlinear Echo Canceller Modes Register (nonlinear_ec_modes) . . . . . . 3.2.11 0x0A--Decision Feedback Equalizer Modes Register (dfe_modes) . . . . . . . . . . . 3.2.12 0x0B--Transmitter Modes Register (transmitter_modes) . . . . . . . . . . . . . . . . . . 3.2.13 0x0C--Timer Restart Register (timer_restart) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.14 0x0D--Timer Enable Register (timer_enable). . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.15 0x0E--Timer Continuous Mode Register (timer_continuous) . . . . . . . . . . . . . . . 3.2.16 0x0F--Test Register (reserved2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.17 0x10, 0x11--Startup Timer 1 Interval Register (sut1_low, sut1_high). . . . . . . . . 3.2.18 0x12, 0x13--Startup Timer 2 Interval Register (sut2_low, sut2_high). . . . . . . . . 3.2.19 0x14, 0x15--Startup Timer 3 Interval Register (sut3_low, sut3_high). . . . . . . . . 3.2.20 0x16, 0x17--Startup Timer 4 Interval Register (sut4_low, sut4_high). . . . . . . . . 3.2.21 0x18, 0x19--Meter Timer Interval Register (meter_low, meter_high) . . . . . . . . . 3.2.22 0x20--Test Register (reserved9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.23 0x1A, 0x1B--SNR Alarm Timer Interval Register (snr_timer_low, snr_timer_high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.24 0x1C, 0x1D--General Purpose Timer 3 Interval Register (t3_low, t3_high) . . . . . 3.2.25 0x1E, 0x1F--General Purpose Timer 4 Interval Register (t4_low, t4_high) . . . . . 3.2.26 0x21--ADC Control Register (adc_control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.27 0x22--PLL Modes Register (pll_modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.28 0x23--Test Register (reserved10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.29 0x24, 0x25--Timing Recovery PLL Phase Offset Register (pll_phase_offset_low, pll_phase_offset_high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.30 0x26, 0x27--Receiver DC Offset Register (dc_offset_low, dc_offset_high) . . . . . 3.2.31 0x28--Transmitter Calibration Register (tx_calibrate) . . . . . . . . . . . . . . . . . . . . . 3.2.32 0x29--Transmitter Gain Register (tx_gain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.33 0x2A, 0x2B--Noise-Level Histogram Threshold Register (noise_histogram_th_low, noise_histogram_th_high) . . . . . . . . . . . . . . . . . . . 3.2.34 0x2C, 0x2D--Error Predictor Pause Threshold Register (ep_pause_th_low, ep_pause_th_high). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.35 0x2E--Scrambler Synchronization Threshold Register (scr_sync_th) . . . . . . . . . 3.2.36 0x30, 0x31--Far-End High Alarm Threshold Register (far_end_high_alarm_th_low, far_end_high_alarm_th_high) . . . . . . . . . . . . . . 3.2.37 0x32, 0x33--Far-End Low Alarm Threshold Register (far_end_low_alarm_th_low, far_end_low_alarm_th_high) . . . . . . . . . . . . . . . 3.2.38 0x34, 0x35--SNR Alarm Threshold Register (snr_alarm_th_low, snr_alarm_th_high). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.39 0x36, 0x37--Cursor Level Register (cursor_level_low, cursor_level_high) . . . . . 3.2.40 0x38, 0x39--DAGC Target Register (dagc_target_low, dagc_target_high). . . . . . 3.2.41 0x3A--Symbol Detector Modes Register (detector_modes) . . . . . . . . . . . . . . . . 3.2.42 0x3B--Peak Detector Delay Register (peak_detector_delay) . . . . . . . . . . . . . . . . 3.2.43 0x3C--Digital AGC Modes Register (dagc_modes) . . . . . . . . . . . . . . . . . . . . . . . 3.2.44 0x3D--Feed Forward Equalizer Modes Register (ffe_modes). . . . . . . . . . . . . . . . 3.2.45 0x3E--Error Predictor Modes Register (ep_modes) . . . . . . . . . . . . . . . . . . . . . . 3.2.46 0x40, 0x41--Phase Detector Meter Register (pdm_low, pdm_high) . . . . . . . . . . 3.2.47 0x42--Overflow Meter Register (overflow_meter) . . . . . . . . . . . . . . . . . . . . . . . . 3.2.48 0x44, 0x45--DC Level Meter Register (dc_meter_low, dc_meter_high) . . . . . . . 49 50 50 52 52 53 53 53 53 53 53 53 54 54 54 54 55 56 57 57 57 57 58 59 59 59 59 59 60 60 60 61 62 62 63 63 64 64 64 N8960DSB v Table of Contents BT8960 Single-Chip 2B1Q Transceiver 3.2.49 0x46, 0x47--Signal Level Meter Register (slm_low, slm_high) . . . . . . . . . . . . . . 3.2.50 0x48, 0x49--Far-End Level Meter Register (felm_low, felm_high). . . . . . . . . . . . 3.2.51 0x4A, 0x4B--Noise Level Histogram Meter Register (noise_histogram_low, noise_histogram_high) . . . . . . . . . . . . . . . . . . . . . . . . 3.2.52 0x4C, 0x4D--Bit Error Rate Meter Register (ber_meter_low, ber_meter_high). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.53 0x4E--Symbol Histogram Meter Register (symbol_histogram). . . . . . . . . . . . . . 3.2.54 0x50, 0x51--Noise Level Meter Register (nlm_low, nlm_high) . . . . . . . . . . . . . . 3.2.55 0x5E, 0x5F-- PLL Frequency Register (pll_frequency_low, pll_frequency_high). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.56 0x70--LEC Read Tap Select Register (linear_ec_tap_select_read). . . . . . . . . . . . 3.2.57 0x71--LEC Write Tap Select Register (linear_ec_tap_select_write) . . . . . . . . . . . 3.2.58 0x72--NEC Read Tap Select Register (nonlinear_ec_tap_select_read) . . . . . . . . 3.2.59 0x73--NEC Write Tap Select Register (nonlinear_ec_tap_select_write). . . . . . . . 3.2.60 0x74--DFE Read Tap Select Register (dfe_tap_select_read) . . . . . . . . . . . . . . . . 3.2.61 0x75--DFE Write Tap Select Register (dfe_tap_select_write). . . . . . . . . . . . . . . . 3.2.62 0x76--Scratch Pad Read Tap Select (sp_tap_select_read) . . . . . . . . . . . . . . . . . 3.2.63 0x77--Scratch Pad Write Tap Select (sp_tap_select_write) . . . . . . . . . . . . . . . . . 3.2.64 0x78--Equalizer Read Select Register (eq_add_read) . . . . . . . . . . . . . . . . . . . . . 3.2.65 0x79--Equalizer Write Select Register (eq_add_write) . . . . . . . . . . . . . . . . . . . . 3.2.66 0x7A--Equalizer Microcode Read Select Register (eq_microcode_add_read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.67 0x7B--Equalizer Microcode Write Select Register (eq_microcode_add_write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.68 0x7C-0x7F--Access Data Register (access_data_byte3:0) . . . . . . . . . . . . . . . . . 65 65 65 66 66 66 67 67 67 67 68 68 68 68 69 69 70 70 70 70 4.0 Electrical & Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.2 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.3 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.4 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.5 Channel Unit Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.6 Microcomputer Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1 Test and Diagnostic Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2 Analog Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.3 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 84 86 89 4.7 Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.8 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 vi N8960DSB BT8960 Single-Chip 2B1Q Transceiver List of Figures List of Figures Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 2-8. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 4-8. Figure 4-9. Figure 4-10. Figure 4-11. Figure 4-12. Figure 4-13. Figure 4-14. Figure 4-15. Figure 4-16. Figure 4-17. Figure 4-18. Figure 4-19. Figure 4-20. 2B1Q Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 BT8960 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 PCM6 Voice Pairgain Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Transmit Section Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 First-Order Echo Cancellation Using the Variable Gain Amplifier . . . . . . . . . . . . . . . . . . . 19 Receiver Digital Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Digital Front-End Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Timing Recovery and Clock Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Serial Sign-Bit First Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Parallel Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Parallel Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 MCLK Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Clock Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Channel Unit Interface Timing, Parallel Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Channel Unit Interface Timing, Parallel Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Channel Unit Interface Timing, Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 MCI Write Timing, Intel Mode (MOTEL = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 MCI Write Timing, Motorola Mode (MOTEL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 MCI Read Timing, Intel Mode (MOTEL = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 MCI Read Timing, Motorola Mode (MOTEL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Internal Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 SMON Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Transmitted Pulse Template. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Transmitter Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Standard Output Load (Totem Pole and Three-State Outputs) . . . . . . . . . . . . . . . . . . . . . 90 Open-Drain Output Load (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Input Waveforms for Timing Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Output Waveforms for Timing Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Output Waveforms for Three-state Enable and Disable Tests. . . . . . . . . . . . . . . . . . . . . . 92 100-Pin Plastic Quad Flat Pack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 N8960DSB vii List of Figures BT8960 Single-Chip 2B1Q Transceiver viii N8960DSB BT8960 Single-Chip 2B1Q Transceiver List of Tables List of Tables Table 1-1. Table 1-2. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 3-1. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 4-7. Table 4-8. Table 4-9. Table 4-10. Table 4-11. Table 4-12. Table 4-13. Table 4-14. Table 4-15. Table 4-16. Table 4-17. Table 4-18. Table 4-19. Table 4-20. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hardware Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Symbol Source Selector/Scrambler Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Four-Level Bit-to-Symbol Conversions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Two-Level Bit-to-Symbol Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Two-Level Symbol-to-Bit Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Four-Level Symbol-to-Bit Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Crystal Oscillator Circuit Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Device Identification JTAG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Register Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 External Clock Timing Requirements (MCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 HCLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Symbol Clock (QCLK) Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Channel Unit Interface Timing Requirements, Parallel Master Mode . . . . . . . . . . . . . . . . 76 Channel Unit Interface Switching Characteristics, Parallel Master Mode . . . . . . . . . . . . . 76 Channel Unit Interface Timing Requirements, Parallel Slave Mode . . . . . . . . . . . . . . . . . 77 Channel Unit Interface Switching Characteristics, Parallel Slave Mode . . . . . . . . . . . . . . 77 Channel Unit Interface Timing Requirements, Serial Mode . . . . . . . . . . . . . . . . . . . . . . . 78 Channel Unit Interface Switching Characteristics, Serial Mode . . . . . . . . . . . . . . . . . . . . 78 Microcomputer Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Microcomputer Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Test and Diagnostic Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Test and Diagnostic Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 84 Receiver Analog Requirements and Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Transmitter Analog Requirements and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Transmitted Pulse Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Transmitter Test Circuit Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 N8960DSB ix List of Tables BT8960 Single-Chip 2B1Q Transceiver x N8960DSB 1.0 System Overview 1.1 Functional Summary The BT8960 2B1Q transceiver is an integral component of Rockwell's telecommunications product line. The major building blocks of a 2B1Q terminal are shown in Figure 1-1. Figure 1-1. 2B1Q Terminal Receive Data Transmit Data Framer/ Channel Unit BT8960 Transceiver Transformer and Hybrid Twisted Pair N8960DSB 1 1.0 System Overview 1.1 Functional Summary BT8960 Single-Chip 2B1Q Transceiver The BT8960 comprises five major functions: a transmit section, a receive section, a timing recovery and clock interface, a microcomputer interface, and a test and diagnostic interface. Figure 1-2 details the connections within and between each of these functional blocks. Figure 1-2. BT8960 Detailed Block Diagram Receive Section RXP RXN VGA RXBP RXBN ADC Digital Front End Echo Canceler Equalizer Detector Receive Channel Unit Interface RQ[1]/RDAT RQ[0]/BCLK RBCLK Microcomputer Interface and System Control Timing Recovery/ PLL HCLK QCLK AD[7:0] ADDR[7:0] MUXED MOTEL WR/R/W RD/DS CS ALE RST READY IRQ Control and Status Registers MicroComputer Interface Crystal Amplifier XTALI/MCLK XTALO XOUT Voltage Reference Generator Timers RBIAS VCOMO VCOMI VCCAP VRXP,VRXN VTXP,VTXN Diagnostics SMON JTAG TMS TDI TCK TDO Transmit Section TXP TXN Line Driver PulseShaping Filter VariableGain DAC Symbol Source/ Scrambler Transmit Channel Unit Interface TBCLK TQ[1]/TDAT TQ[0] TXLDIN TXLDIP TXPSN TXPSP 2 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 1.0 System Overview 1.1 Functional Summary 1.1.1 Transmit Section The source of transmitted symbols is programmable through the microcomputer interface. The primary choices include external 2B1Q-encoded data presented to the TQ[1,0]/TDAT pins of the channel unit interface, internally looped-back receive symbols from the detector, or a constant "all ones" source. The symbols are then optionally scrambled. Isolated pulses can also be generated to support the testing of pulse templates. The digital symbols are transformed to an analog signal via the DAC, which is highly linear in order to maximize the echo cancellation and detection properties of the signal. In addition, the transmit power level of the DAC may be adjusted via the Transmitter Gain Register [tx_gain; 0x29] to optimize performance. The Transmitter Calibration Register [tx_calibrate; 0x28] contains the nominal setting for the transmitter gain which is calibrated and hard-coded at the factory. The pulse-shaping filter then conditions the signal to prevent crosstalk to adjacent subscriber lines. Finally, the differential line driver provides the current driving capabilities and low-distortion characteristics needed to drive a large range of subscriber lines at low-bit error rates. 1.1.2 Receive Section The differential Variable Gain Amplifier (VGA) receives the data from the subscriber line. Balancing inputs (RXBP, RXBN) are provided to accommodate firstorder transmit echo cancellation via an external hybrid. The gain is programmable so that the dynamic range of the Analog-to-Digital Converter (ADC) can be maximized according to the attenuation of the subscriber line. Digitized receive data is passed to the Digital Signal Processor (DSP) portion of the BT8960. After DC offset cancellation, a replica of the transmit signal is subtracted from the total receive signal by a digital echo canceler. The resultant farend signal is then conditioned by an equalization stage consisting of Automatic Gain Control (AGC), a feed-forward equalizer, a decision-feedback equalizer, and an error predictor. A mode-dependent detector is then used to recover the 2B1Q-encoded data from the equalized signal. The channel unit interface then provides an optional descrambling function followed by parallel or serial output of the sign and magnitude bits on pins RQ[1,0]/RDAT. A number of meters are implemented within the receiver to provide average level indications at various points in the receive signal path. The receive section also performs remote unit clock recovery through an on-chip Phase Lock Loop (PLL) circuit. 1.1.3 Timing Recovery and Clock Interface The clock interface includes a crystal amplifier module to reduce the external components needed for clock generation. The crystal frequency must be 64 times the desired symbol rate. When configured as a remote unit, the PLL module recovers the incoming data clock and outputs it on the QCLK pin (and also the BCLK pin for serial mode operation). The HCLK output, which is synchronized to the QCLK signal, can be configured to cycle at 16, 32, or 64 times the symbol rate. N8960DSB 3 1.0 System Overview 1.1 Functional Summary BT8960 Single-Chip 2B1Q Transceiver 1.1.4 Microcomputer Interface The Microcomputer Interface (MCI) provides access to a 256-byte address space within the transceiver. A combination of direct and indirect addressing methods are used to access all internal locations. The MCI is designed to interface with both Intel- and Motorola-style processors with no additional glue logic. A MOTEL control pin is provided to configure the bus interface control/handshake lines to conform to common Motorola/Intel conventions. A MUXED control pin is provided to configure the bus interface address and data lines for multiplexed or independent data/address bus operation. Little-endian data formatting (least significant byte of a multibyte word stored at the lowest byte-address location) is used in all cases, regardless of MOTEL pin selection. A READY control pin is provided to support wait-state insertion. An Interrupt Request (IRQ) output pin supports low-latency responses to time-critical events within the transceiver. Eight 16-bit timers and ten measurement meters are integrated into the transceiver. The timers support various metering functions within the receiver section, and off-load the external microcomputer from complex timing operations associated with startup procedures. Control and monitoring access to the timers and meters is provided through the microcomputer interface. 1.1.5 Test and Diagnostic Interface (JTAG) The test and diagnostic interface comprises a test access port and a Serial Monitor Output (SMON). The test access port conforms to IEEE Std 1149.1-1990, (IEEE Standard Test Access Port and Boundary Scan Architecture). Also referred to as Joint Test Action Group (JTAG), this interface provides direct serial access to each of the transceiver's I/O pins. This capability can be used during an in-circuit board test to increase the testability and reduce the cost of the in-circuit test process. The serial monitor output can be viewed as a real-time virtual probe for looking at the transceiver's internal signals. The programmable signal source is shifted out serially at 16 times the symbol rate. The majority of the receive signal path is accessible through this output. 4 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 1.0 System Overview 1.2 Applications 1.2 Applications 1.2.1 Voice/Data Pairgain A well-established market exists for voice pairgain systems. These systems transport several simultaneous phone conversations over a single twisted pair. They are used by telecommunications service providers to maximize the utilization of the existing copper plant, and allow it to provision many more telephone circuits than possible with ordinary 4 kHz analog transport. The external interfaces of voice pairgain systems, at both the central office and remote ends, are analog POTS lines. Various carrier techniques exist to facilitate the single-pair transmission such as: the Frequency Domain Multiplexed (FDM) systems and Time Domain Multiplexed (TDM) systems. In FDM systems, each voice channel is modulated by a successively higher carrier, therefore the composite transmission consists of several frequency bands. In TDM systems, the voice data is digitized and sampled in a channel-multiplexed fashion. Although FDM systems are currently fielded, recent trends are clearly toward TDM systems due to the inherent advantages associated with digital transmission. Traditional 1 + 3, also called PCM4 voice pairgain systems, use a combination of 2:1 ADPCM compression and basic rate ISDN U-interface devices to transport four voice conversations on one twisted pair. The disadvantage of this scheme is that clear 64 kbps channel capacity is lost due to the ADPCM voice compression algorithm. This may prevent high-speed facsimile transmissions from being transported reliably. Regarding the BT8960, an alternate way exists to implement this type of voice pairgain equipment. A BT8960-based system can transport four or six clear 64 kbps channels on a single pair. Clear 64 kbps transport assures the transmission of any baud-rate facsimile or can be used to provision special data services such as switched 56, clear 64, and frame relay. Figure 1-3 shows the architecture of a PCM6 voice pairgain system. As illustrated, six analog Subscriber Line Interface Cards (SLIC) are connected to a concentrating framer. The function of this framer is to time-multiplex the PCM data from the SLICs, create a transport frame, and handle signaling information. The output of the framer is then passed on to the BT8960 for conversion into the 2B1Q code suitable for long-reach transport over the loop plant. N8960DSB 5 1.0 System Overview 1.2 Applications BT8960 Single-Chip 2B1Q Transceiver Figure 1-3. PCM6 Voice Pairgain Block Diagram SLIC SLIC SLIC PCM Framer SLIC BT8960 Local Loop SLIC SLIC 1.2.2 Internet Connectivity Transport The growth of the Internet has created a tremendous demand for additional bandwidth in the local loop. When existing loop facilities are used to provide connectivity to Internet servers, they are limited to the 128 kbps offered by Basic Rate ISDN (BRI) service. Although those same loops could be provisioned through HDSL (for E1 or T1 transport rates), the tariff structure for these services puts their bandwidth beyond the practical reach of most consumers. It is unlikely that the E1/T1 tariff structure will change soon since it still represents significant value for business customers using E1/T1 leased lines for corporate data and voice exchange. The 128 kbps rate offered by BRI is sufficient for the text and graphic content of most of today's home pages. However, when motion, video, or interactivity are added, the data rate required is increased to well over 300 kbps. The advent of the BT8960 creates an intermediate solution between BRI and E1/T1 which opens a host of low-cost, higher bandwidth possibilities. With the BT8960, local loops could be provisioned for data rates up to 384 kbps with lowcost hardware. In addition, the full ISDN 18,000 ft. carrier service area could be served with a higher data rate. Enabling hardware could, for example, take the form of LAN extender equipment, and terminals for such equipment could have standard Ethernet connections to routers, personal computers, or workstations. The terminals could also use the BT8960 2B1Q transport mechanism for the local loop link to the central office or Internet server location. By placing a SLIC in the terminal and reserving a 64 kbps channel for voice transport, simultaneous data and voice service could be offered over a single twisted pair. The extraordinary low power of the BT8960 allows for customer site equipment to be remotely powered, thereby guaranteeing lifeline POTS service in the event of power loss at the customer site. 6 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 1.0 System Overview 1.2 Applications 1.2.3 ISDN Basic Rate Interface Concentrator Since many telecommunications service providers are positioning BRI service as residential Internet or telecommuter connectivity, the lack of installed copper pairs into the residence could be a serious limitation to the proliferation of the service. The BT8960 solves this problem because it is capable of 416 kbps data rates. Thus, it enables the transport of two full BRI U-interface channels (4B + 2D) on a single twisted pair. Alternatively, a BRI service and two POTS lines can be provisioned over a single twisted pair. Another possible combination is six B-channels with a consolidated D-channel for the provisioning of three ISDN lines on a single twisted pair. Users of this equipment can include a small office with two computers, each needing BRI service, or a residence requiring a BRI line and two POTS lines. The primary advantage of (1 or 2 BRIs + 1 or 2 POTS) is there is no need for expensive digital phones and when a POTS function is used, the full BRI bandwidth for data traffic is retained. N8960DSB 7 1.0 System Overview 1.3 Pin Descriptions BT8960 Single-Chip 2B1Q Transceiver 1.3 Pin Descriptions The BT8960 is packaged in a 100-Pin Plastic Quad Flat Pack (PQFP). The pin assignments are shown in Figure 1-4. A listing of pin labels, numbers, and I/O assignments is given in Table 1-1. Signal definitions are provided in Table 1-2. The coding used in the I/O column is: O = digital output, OA = analog output, OD = open-drain output, I = digital input, IA = analog input, and I/O = bidirectional. Figure 1-4. Pin Diagram DGND DGND VDD2 TCK TMS TDI TDO DTEST6 DTEST5 TBCLK RBCLK RQ[0]/BCLK RQ[1]/RDAT QCLK TQ[0] TQ[1]/TDAT DGND VDD1 AGND VAA VDD1 CS RD/DS WR/R/W ALE IRQ READY AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] DGND DGND VDD2 AD[7] MOTEL MUXED ADDR[7] ADDR[6] ADDR[5] ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0] SMON VDD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 BT8960 8 DGND DGND VDD2 RST HCLK XOUT DGND VDD1 XTALO XTALI/MCLK VDD2 DGND DTEST1 DTEST2 DTEST3 VDD1 DGND DTEST4 AGND AGND 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 RXBN RXBP RXN RXP AGND AGND TXN AGND VAA TXP TXLDIN TXLDIP TXPSN TXPSP ATEST2 ATEST1 VAA VAA AGND VTXN VTXP VCCAP VCOMO VCOMI RBIAS VAA VAA AGND VRXN VRXP N8960DSB BT8960 Single-Chip 2B1Q Transceiver Table 1-1. Pin Descriptions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1.0 System Overview 1.3 Pin Descriptions Pin Label VDD1 CS RD/DS WR/R/W ALE IRQ READY AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] DGND DGND VDD2 AD[7] MOTEL MUXED ADDR[7] ADDR[6] ADDR[5] ADDR[4] ADDR[3] I/O - I I I I OD OD I/O I/O I/O I/O I/O I/O I/O - - - I/O I I I I I I I Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin Label ADDR[2] ADDR[1] ADDR[0] SMON VDD1 DGND DGND VDD2 RST HCLK XOUT DGND VDD1 XTALO XTALI/MCLK VDD2 DGND DTEST1 DTEST2 DTEST3 VDD1 DGND DTEST4 AGND AGND I/O I I I O - - - - I O O - - O I - - I I I - - I - - Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin Label VRXP VRXN AGND VAA VAA RBIAS VCOMI VCOMO VCCAP VTXP VTXN AGND VAA VAA ATEST1 ATEST2 TXPSP TXPSN TXLDIP TXLDIN TXP VAA AGND TXN AGND I/O OA OA - - - OA OA OA OA OA OA - - - IA IA OA OA IA IA OA - - OA - Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Label AGND RXP RXN RXBP RXBN VAA AGND VDD1 DGND TQ[1]/TDAT TQ[0] QCLK RQ[1]/RDAT RQ[0]/BCLK RBCLK TBCLK DTEST5 DTEST6 TDO TDI TMS TCK VDD2 DGND DGND I/O - IA IA IA IA - - - - I I O O O I I I I O I I I - - - N8960DSB 9 1.0 System Overview 1.3 Pin Descriptions BT8960 Single-Chip 2B1Q Transceiver Table 1-2. Hardware Signal Definitions (1 of 4) Pin Label Signal Name I/O Microcomputer Interface (MCI) MOTEL Motorola/Intel I Selects between Motorola and Intel handshake conventions for the RD/DS and WR/R/W signals. MOTEL = 1 for Motorola protocol: DS, R/W MOTEL = 0 for Intel protocol: RD, WR Falling-edge-sensitive input. The value of AD[7:0] when MUXED = 1, or ADDR[7:0] when MUXED = 0, is internally latched on the falling edge of ALE. Active-low input used to enable read/write operations on the Microcomputer Interface (MCI). Bimodal input for controlling read/write access on the MCI. When MOTEL = 1 and CS = 0, RD/DS behaves as an active-low data strobe DS. Internal data is output on AD[7:0] when DS = 0 and R/W = 1. External data is internally latched from AD[7:0] on the rising edge of DS when R/W = 0. When MOTEL = 0 and CS = 0, RD/DS behaves as an active-low read strobe RD. Internal data is output on AD[7:0] when RD = 0. Write operations are not controlled by RD in this mode. Bimodal input for controlling read/write access on the MCI. When MOTEL = 1 and CS = 0, WR/R/W behaves as a read/write select line R/W. Internal data is output on AD[7:0] when DS = 0 and R/W = 1. External data is internally latched from AD[7:0] on the rising edge of DS when R/W = 0. When MOTEL = 0 and CS = 0, WR/R/W behaves as an active-low write strobe WR. External data is internally latched from AD[7:0] on the rising edge of WR. Read operations are not controlled by WR in this mode. 8-bit bidirectional multiplexed address-data bus. AD[7] = MSB, AD[0] = LSB. Usage is controlled using the MUXED signal as defined below. Provides a glueless interface to microcomputers with separate address and data buses. ADDR[7] = MSB, ADDR[0] = LSB. Usage is controlled using the MUXED signal. Controls the MCI addressing mode. When MUXED = 1, the MCI uses AD[7:0] as a multiplexed signal for address and data (typical of Intel processors). When MUXED = 0, the MCI uses ADDR[7:0] as the address input and AD[7:0] for data only (typical of Motorola processors). Active-low, open-drain output that indicates that the MCI is ready to transfer data. Can be used to signal the microcomputer to insert wait states. Active-low, open-drain output that indicates requests for interrupt. Asserted whenever at least one unmasked interrupt flag is set. Remains inactive whenever no unmasked interrupt flags are present. Asynchronous, active-low, level-sensitive input that places the transceiver in an inactive state by setting the power-down mode bit of the Global Modes and Status Register [global_modes; 0x00], and zeroing the clk_freq[1,0] bits of the PLL Modes Register [pll_modes; 0x22], and the hclk_freq[1,0] bits of the Serial Monitor Source Select Register [serial_monitor_source; 0x01]. All RAM contents are lost. Does not affect the state of the test access port which is reset automatically at power-up only. Definition ALE CS RD/DS Address Latch Enable Chip Select Read/Data Strobe I I I WR / R/W Write/ Read/Write I AD[7:0] ADDR[7:0] AddressData[7:0] Address Bus[7:0] (Not Multiplexed) Addressing Mode Select I/O I MUXED I READY IRQ Ready Interrupt Request OD OD RST Reset I 10 N8960DSB BT8960 Single-Chip 2B1Q Transceiver Table 1-2. Hardware Signal Definitions (2 of 4) Pin Label Signal Name I/O Channel Unit Interface RQ[1]/ RDAT RQ[0]/ BCLK Receive Quat 1/ Receive Data Receive Quat 0/ Bit Clock O 1.0 System Overview 1.3 Pin Descriptions Definition O RQ[1]/RDAT and RQ[0]/BCLK are bimodal outputs that represent the sign and magnitude bits of the received quaternary output symbol in parallel channel unit modes (RQ[1], RQ[0]), and the serial-data and bit-clock outputs in serial channel unit modes (RDAT, BCLK). Behavior of these outputs is configurable through the Channel Unit Interface Modes Register [CU_interface_modes; 0x06] for parallel master, parallel slave, serial magnitude-bit-first and serial sign-bit-first operations. For parallel mode operation: RQ[1] = Sign bit output RQ[0] = Magnitude bit output Both outputs are updated at the symbol rate on the rising edge of QCLK (master mode) or the rising/falling edge (programmable) of RBCLK (slave mode). For serial mode operation: RDAT = Serial quaternary data output BCLK = Bit-rate (two times symbol rate) clock output RDAT is updated at the bit rate on the rising edge of BCLK TQ[1]/ TDAT TQ[0] Transmit Quat 1/ Transmit Data Transmit Quat 0 I I TQ[1]/TDAT and TQ[0] are bimodal inputs that represent the sign and magnitude bits of the quaternary input symbol to be transmitted in parallel channel unit modes (TQ[1], TQ[0]), and the serial data input in serial channel unit modes (TDAT). Interpretation of these inputs is configurable through the Channel Unit Interface Modes Register [CU_Interface_modes; 0x06] for parallel master, parallel slave, serial magnitude-bit-first and serial sign-bit-first operations. For parallel mode operation: TQ[1] = Sign bit input TQ[0] = Magnitude bit input Both inputs are sampled at the symbol rate on the falling edge of QCLK (master mode) or the rising/falling edge (programmable) of TBCLK (slave mode). For serial mode operation: TDAT = Serial quaternary data input TQ0 = Don't care (tie or pull up to supply rail) TDAT is sampled at the bit rate (two times the symbol rate) on the falling edge of BCLK. QCLK TBCLK Quaternary Clock Transmit BaudRate Clock Receive BaudRate Clock O I Runs at the symbol rate. It defines the data on the TQ and RQ interfaces. QCLK is also used to frame transmit/receive quats in serial mode. Functions as the transmit baud-rate clock input. It must be frequency locked to QCLK. This input is used only when the channel unit interface is in parallel slave mode. If it is unused, it should be tied to VDD2 or DGND. Functions as the receive baud-rate clock input. It must be frequency locked to QCLK. This input is used only when the channel unit interface is in parallel slave mode. If it is unused, it should be tied to VDD2 or DGND. RBCLK I N8960DSB 11 1.0 System Overview 1.3 Pin Descriptions BT8960 Single-Chip 2B1Q Transceiver Table 1-2. Hardware Signal Definitions (3 of 4) Pin Label Signal Name I/O Analog Transmit Interface TXP, TXN TXLDIP, TXLDIN TXPSP, TXPSN Transmit Positive, Negative Transmit Line Driver In Positive, Negative Transmit PulseShaping Filter Positive, Negative OA IA Differential Transmit Line Driver Outputs. These signals are used to drive the subscriber line after passing through the hybrid and line transformer. Differential Transmit Line Driver Inputs. These inputs should be connected to the TXPSP, TXPSN outputs after passing through an external RC filter. Differential Transmit Pulse-shaping Filter Outputs. These outputs should be connected to an external RC filter, which is then connected to the TXLDIP and TXLDIN inputs. Definition OA Analog Receive Interface RXP, RXN RXBP, RXBN Receive Positive, Negative Receive Balance Positive, Negative IA IA Differential Receiver Inputs. RXP and RXN receive the signal from the subscriber line. Differential Receiver Balance Inputs. RXBP and RXBN are used to subtract the echo of the signal being transmitted on the subscriber line. They should be connected to the TXP, TXN output pins through the hybrid circuit. This signal is subtracted from the signal being received by the RXP and RXN inputs in the Variable Gain Amplifier (VGA). Voltage Reference Generator Interface RBIAS VCOMO VCOMI VCCAP VRXP, VRXN Resistor Bias Common Mode Voltage Outputs Common Mode Voltage Inputs Voltage Compensation Capacitor Receiver Voltage Reference Positive, Negative Transmit Voltage Reference Positive, Negative OA OA OA OA OA Connection point for external bias resistor. Common mode voltage for the analog circuitry. This pin should be connected to an external filtering capacitor. Common mode voltage for the analog circuitry. This pin should be connected to an external filtering capacitor. Analog Voltage Compensation Capacitor. This pin should be connected to an external filtering capacitor. Analog Receive Circuitry Reference Voltages. These pins should be connected to external filtering capacitors. Analog Transmit Circuitry Reference Voltages. These pins should be connected to external filtering capacitors. VTXP, VTXN OA Clock Interface XTALI/ MCLK Crystal In/Master Clock I A bimodal input that can be used as the crystal input or as the master clock input. If an external clock is connected to this input, XTALO should be left floating. The frequency of the crystal or clock should be 64 times the symbol rate (32 times the data rate). Connection point for the crystal. HCLK can be configured to run at 16, 32, or 64 times the symbol rate. Upon reset, it is set to 64 times the symbol rate. This clock will be phase locked to the incoming data when the BT8960 is configured as the remote unit. Buffered-crystal oscillator output. XTALO HCLK Crystal Output High Speed Clock Out Crystal Clock Out O O XOUT O 12 N8960DSB BT8960 Single-Chip 2B1Q Transceiver Table 1-2. Hardware Signal Definitions (4 of 4) Pin Label Signal Name I/O Test and Diagnostic Interface TDI JTAG Test Data Input I 1.0 System Overview 1.3 Pin Descriptions Definition JTAG test data input per IEEE Std 1149.1-1990. Used for loading all serial instructions and data into internal test logic. Sampled on the rising edge of TCK. TDI can be left unconnected if it is not being used because it is pulled-up internally. JTAG test mode select input per IEEE Std 1149.1-1990. Internally pulled-up input signal used to control the test-logic state machine. Sampled on the rising edge of TCK. TMS can be left unconnected if it is not being used because it is pulled-up internally. JTAG test data output per IEEE Std 1149.1-1990. Three-state output used for reading all serial configuration and test data from internal test logic. Updated on the falling edge of TCK. JTAG test clock input per IEEE Std 1149.1-1990. Used for all test interface and internal test logic operations. If unused, TCK should be pulled low. Serial data output used for real-time monitoring of internal signal-path registers. The source register is selected through the Serial Monitor Source Select Register [serial_monitor_source; 0x01]. 16-bit words are shifted out, LSB first, at 16 times the symbol rate. The rising edge of QCLK defines the start Least Significant Bit (LSB) of each word. The output is updated on the rising edge of an internal clock running at 16 times QCLK. Active-high test inputs used by Rockwell to enable internal test modes. These inputs should be tied to digital ground (DGND). Active-low test inputs used by Rockwell to enable internal test modes. These inputs should be tied to the I/O buffer power supply (VDD2). Analog test inputs used by Rockwell for internal test modes. These inputs should be left floating (No Connect, NC). TMS JTAG Test Mode Select I TDO JTAG Test Data Output JTAG Test Clock Input Serial Monitor O TCK SMON I O DTEST[1:4] DTEST[5, 6] ATEST[1,2] Digital Tests 1-4 Digital Test 5, 6 Analog Test 1, 2 I I IA Power and Ground VDD1 VDD2 DGND VAA AGND Core Logic Power Supply I/O Buffer Power Supply Digital Ground Analog Power Supply Analog Ground - - - - - Dedicated supply pins powering the digital core logic functions. Dedicated supply pins powering the digital I/O buffers. Dedicated ground pins for the digital circuitry. Must be held at same potential as AGND. Dedicated supply pins powering the analog circuitry. Dedicated ground pins for the analog circuitry. Must be held at the same potential as DGND. N8960DSB 13 1.0 System Overview 1.3 Pin Descriptions BT8960 Single-Chip 2B1Q Transceiver 14 N8960DSB 2.0 Functional Description 2.1 Transmit Section The transmit section is illustrated in Figure 2-1. It comprises four major functions: a symbol source selector/scrambler, a variable gain digital-to-analog converter (DAC), a pulse-shaping filter, and a line driver. Figure 2-1. Transmit Section Block Diagram Transmit Channel Unit Interface TQ[1,0] Symbol Source/ Scrambler Variable-Gain DAC PulseShaping Filter Line Driver TXP TXN Isolated Pulses Detector Loopback Ones (1s) Control Registers External RC Filter N8960DSB 15 2.0 Functional Description 2.1 Transmit Section BT8960 Single-Chip 2B1Q Transceiver 2.1.1 Symbol Source Selector/Scrambler The input source selector/scrambler can be configured through the Transmitter Modes Register [transmitter_modes; 0x0B] data_source [2:0] bits to select the source of the data to be transmitted and determine whether or not the data is scrambled. The symbol source selector/scrambler modes are specified in Table 21. Table 2-1. Symbol Source Selector/Scrambler Modes data_source[2:0] 000 001 010 011 100 101 110 Symbol Source Selector/Scrambler Mode Isolated pulse. Level selected by isolated_pulse[1,0]. The meter timer must be enabled and in the continuous mode. The pulse repetition interval is determined by the meter-timer-countdown interval. Four-level scrambled detector loopback. Sign and magnitude bits from the receiver detector are scrambled and looped back to the transmitter. Feedback polynomial determined by the htur_lfsr control bit. Four-level unscrambled data. Transmits the four-level (2B1Q) sign and magnitude bits from the transmit channel unit. Four-level scrambled ones. Transmits a scrambled, constant high-logic level as a four-level (2B1Q) signal. Feedback polynomial determined by the htur_lfsr control bit. Reserved. Four-level scrambled data. Scrambles and transmits the four-level (2B1Q) sign and magnitude bits from the channel unit transmit interface. Feedback polynomial determined by the htur_lfsr control bit. Two-level unscrambled data. Constantly forces the magnitude bit from the transmit channel unit interface to a logic zero, and transmits the resulting two-level signal (as determined by the sign bit) without scrambling. Valid output levels limited to +3, -3. Two-level scrambled ones. Transmits a scrambled, constant high-logic level, as a two-level signal. Feedback polynomial determined by the htur_lfsr control bit. Scrambler is run at the symbol rate (half-bit rate) to produce the sign bit of the transmitted signal while the magnitude bit is sourced with a constant logic zero. Valid output levels limited to +3, -3. 111 16 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 2.0 Functional Description 2.1 Transmit Section The bit stream is converted into symbols for the four-level cases as shown in Table 2-2. Table 2-2. Four-Level Bit-to-Symbol Conversions First Input Bit (sign) 0 0 1 1 Second Input Bit (magnitude) 0 1 1 0 Output Symbol -3 -1 +1 +3 In two-level mode, the magnitude bit is forced to a zero. This forces the symbols to be +3 and -3, as shown in Table 2-3. Table 2-3. Two-Level Bit-to-Symbol Conversions First Input Bit (sign) 0 1 Second Input Bit (magnitude) don't care don't care Output Symbol -3 +3 The scrambler is essentially a 23-bit-long Linear Feedback Shift Register (LFSR). The feedback points are programmable for central office and remote terminal applications using the htur_lfsr bit of the Transmitter Modes Register. The LFSR polynomials for local (HTU-C/LTU) and remote (HTU-R/NTU) unit operations are: local x -23 x -5 1 remote x -23 x -18 1 The scrambler operates differently depending on whether a two-level or fourlevel mode is specified. In 2-level scrambled-ones mode, the LFSR is clocked once-per-symbol; in 4-level mode, the LFSR is clocked twice-per-symbol. The Transmitter Modes Register can also be used to zero the output of the transmitter using the transmitter_off control bit. The BT8960 can generate isolated pulses to support the testing of pulse templates. When in the isolated pulse mode, the output consists of a single pulse surrounded by zeros. NOTE: Zero is not a valid 2B1Q level and only occurs in this special mode or when the transmitter is off. The repetition rate of the pulses is controlled by the meter timer. Any of the four 2B1Q levels may be chosen via the Transmitter Modes Register's isolated_pulse[1,0] control bits. N8960DSB 17 2.0 Functional Description 2.1 Transmit Section BT8960 Single-Chip 2B1Q Transceiver 2.1.2 Variable Gain Digital-to-Analog Converter A four-level Digital-to-Analog Converter (DAC) is integrated into the BT8960 to accurately convert the output of the symbol source to analog form. The normalized values of these four analog levels are: +3, +1, -1 and -3. Each represents a symbol or quat. To provide precise adjustment of the transmitted power, the level of the DAC may be adjusted. The Transmitter Gain Register [tx_gain; 0x29] sets the level. During the manufacturing of the BT8960, one source of variation in the transmitter levels is process variations. The Transmitter Calibration Register [tx_calibrate; 0x28] contains a read-only value which nulls this variation. The value of this register is determined for each BT8960 device during production testing. Upon initialization, the Transmitter Gain Register should be loaded based on the Transmitter Calibration Register. If there are other sources of transmit power variation (e.g., a nonstandard hybrid or attenuative lightening protection), the transmitter gain must be adjusted to include these affects. 2.1.3 Pulse-Shaping Filter The pulse-shaping filter filters the quats output from the variable-gain DAC. This filter, when combined with other filtering in the signal path, produces a transmitted signal on the line that meets the power spectral density, transmitted power, and pulse-shaping requirements, as specified in the Electrical Specifications section of this datasheet. 2.1.4 Line Driver The line driver buffers the output of the pulse-shaping filter to drive diverse loads. The output of the line driver is differential. 18 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 2.0 Functional Description 2.2 Receive Section 2.2 Receive Section Like the transmit section, the receive section consists of both analog and digital circuitry. The VGA provides the interface to the analog signals received from the line and the hybrid. The Analog-to-Digital Converter (ADC) then digitizes the analog signal so it can be further processed in the digital signal Processing (DSP) section of the receiver. The receiver DSP section includes: front-end processing, echo cancellation, equalization, and symbol detection. 2.2.1 Variable Gain Amplifier The Variable Gain Amplifier (VGA) has two purposes. The first is to provide a dual-differential analog input so the pseudo-transmit signal created by the hybrid can be subtracted from the signal from the line transformer. This subtraction provides first-order echo cancellation, which results in a first-order approximation of the signal received from the line. Figure 2-1 illustrates the recommended suggested echo-cancellation circuit interconnections. All off-chip circuitry, including the hybrid and anti-alias filters, consists entirely of passive components. Further echo cancellation occurs in the receiver DSP. Figure 2-2. First-Order Echo Cancellation Using the Variable Gain Amplifier Line + Transformer - Line (Twisted Pair) RXP Anti-Alias Filter RXN TXP TXN Line Impedance Matching Resistors RXBP Hybrid Anti-alias Filter RXBN + - + Line - Driver + - Gain[2:0] To ADC + - + - Off-Chip Circuitry On-Chip Circuitry The second purpose of the VGA is to provide programmable gain of the received signal prior to passing it to the ADC. This reduces the resolution required for the ADC. There are six gain settings ranging from 0 dB to 15 dB. The gain is controlled via the gain[2:0] control bits in the ADC Control Register [adc_control; 0x21]. See the Registers section of this datasheet for a more detailed description of the gain[2:0] control bits. N8960DSB 19 2.0 Functional Description 2.2 Receive Section BT8960 Single-Chip 2B1Q Transceiver 2.2.2 Analog-to-Digital Converter The ADC provides 16 bits of resolution. The analog input from the variable gain amplifier is converted into digital data and output at the symbol rate. 2.2.3 Digital Signal Processor The Digital Signal Processor (DSP) includes five Least Mean Squared (LMS) filters: an Echo Canceller (EC), a Digital Automatic Gain Controller (DAGC), a Feed Forward Equalizer (FFE), an Error Predictor (EP), and a Decision Feedback Equalizer (DFE). These filters are used to equalize the received signal so that the symbols transmitted from the far-end can be reliably recovered. The DSP uses symbol rate sampling for all processing functions. Their interconnections and relationships to the digital front-end and the detector are illustrated in Figure 2-3. Figure 2-3. Receiver Digital Signal Processing Detector - PKD Digital Front-End DAGC FFE Slicer Channel Unit Interface - - - - - NEC EP LEC Transmit Symbol DFE Echo Canceller Equalizer 20 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 2.0 Functional Description 2.2 Receive Section 2.2.3.1 Digital Front-End Prior to the main signal processing, the input signal must be adjusted for any DC offset. The front-end module also monitors the input signal level, which includes measuring DC and AC input signal levels, detecting and counting overflows, and detecting alarms based on the far-end signal level. Figure 2-4 summarizes the features of the digital front-end module. Figure 2-4. Digital Front-End Block Diagram Echo-Free Signal from NEC Absolute Value High Threshold from MCI Comparator high_felm Interrupt Accumulator Low Threshold from MCI Comparator low_felm Interrupt Result Register Far-End Level Meter ADC Data + - Accumulator DC Offset from MCI Result Register Accumulator Absolute Value r, To EC Far-End Alarms Result Register DC Level Meter Signal Level Meter Overflow Overflow Detector Counter Result Register Overflow Monitor N8960DSB 21 2.0 Functional Description 2.2 Receive Section BT8960 Single-Chip 2B1Q Transceiver 2.2.3.2 Offset Adjustment A nonzero DC level on the input can be corrected by a DC offset value [dc_offset_low, dc_offset_high; 0x26, 0x27] which is subtracted from the input. The DC offset is a 16-bit number and is programmed via the microcomputer interface. The DC level meter provides the monitoring needed for adaptive offset compensation. The offset-adjusted input signal is accumulated over the meter timer interval [meter_low, meter_high; 0x18, 0x19]. The 16 MSBs are placed into the DC Level Meter Registers [dc_meter_low, dc_meter_high; 0x44, 0x45]. The signal level meter provides the monitoring needed for adjusting the analog gain circuit located prior to the ADC. This value is accumulated over the meter timer interval [meter_low, meter_high; 0x18, 0x19]. The 16 MSBs are placed in the Signal Level Meter Registers [slm_low, slm_high; 1; 0x46, 0x47]. The overflow sensor detects ADC overflows. The overflow monitor counts the number of overflows, as indicated by the overflow sensor during the meter timer interval [meter_low, meter_high; 0x18, 0x19]. The counter is limited to 8 bits. In the case of 256 or more overflows during the measurement interval, the counter will hold at 255. The counter is loaded into the Overflow Meter Register [overflow_meter; 0x42] at the end of each measurement interval. The far-end level meter monitors the output of the echo canceler. Since the echo canceler output had the echo of the transmitted signal subtracted from it, it is called the far-end signal. This value is accumulated over the meter timer interval [meter_low, meter_high; 0x18, 0x19]. The 16 MSBs are placed into the Far-End Level Meter Register [felm_low, felm_high; 0x48, 0x49]. The result of the far-end level meter is compared to two thresholds. When exceeded, an interrupt is sent to the microcomputer interface, if enabled. The threshold is determined by the value in the Far-End High Alarm Threshold Registers [far_end_high_alarm_th_low, far_end_high_alarm_th_high; 0x30, 0x31] and the Far-End Low Alarm Threshold Registers [far_end_low_alarm_th_low, far_end_low_alarm_th_high; 0x32, 0x33]. The interrupts high_felm and low_felm, are bits 2 and 1, respectively of the IRQ Source Register [irq_source; 0x05]. The interrupts high_felm and low_felm, can be masked by writing a one to bits 2 and 1, respectively of the Interrupt Mask Register High [mask_high_reg; 0x03]. 2.2.3.3 DC Level Meter 2.2.3.4 Signal Level Meter 2.2.3.5 Overflow Detection and Monitoring 2.2.3.6 Far-End Level Meter 2.2.3.7 Far-End Level Alarm 22 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 2.0 Functional Description 2.2 Receive Section 2.2.4 Echo Canceler The EC removes images of the transmitted symbols from the received signal and consists of two blocks: a linear and nonlinear echo canceler. The organization of the blocks is displayed in Figure 2-3. 2.2.4.1 Linear Echo Canceler (LEC) The Linear Echo Canceler (LEC) is a conventional LMS Finite Impulse Response (FIR) filter, which removes linear images of the transmitted symbols from the received signal. It consists of a 60-tap FIR filter with 32-bit linear adapted coefficients. When enabled, the last data tap of the echo canceler is treated specially. This serves to cancel any DC offset that may be present. A freeze coefficient mode may be specified via the microcomputer interface. This mode disables the coefficient updates only. A special mode exists to zero all of the coefficients; it is also enabled through the microcomputer interface. An additional mode exists to zero the output of the FIR with no effect on the coefficients. It is also enabled through the microcomputer interface. Individual EC coefficients can be read and written through the microcomputer interface. Adaptation should be frozen prior to reading or writing coefficients. The Nonlinear Echo Canceler (NEC) reduces the residual echo power in the echo canceler output caused by nonlinear effects in the transmitter DAC, receiver ADC, analog hybrid circuitry, or line cables. The delay of the transmit-symbol input to the NEC can be specified via the microcomputer interface: Nonlinear Echo Canceler Mode Register [nonlinear_ec_modes; 0x09]. This allows the NEC to operate on the peak of the echo regardless of differing delays in the echo path. A freeze coefficient mode may be specified via the microcomputer interface. This mode disables the coefficient updates only. A special mode exists to zero all of the coefficients; it is also enabled through the microcomputer interface. An additional mode exists to zero the output of the look-up table with no effect on the coefficients. It is also enabled through the microcomputer interface. The 64, 14-bit, individual NEC coefficients can be read and written through the microcomputer interface. Adaptation should be frozen prior to reading or writing coefficients. 2.2.4.2 Nonlinear Echo Canceler (NEC) 2.2.5 Equalizer Four LMS filters are used in the equalizer to process the echo canceler output so that received symbols can be reliably recovered. The filters are a digital automatic gain controller, a feed forward equalizer, an error predictor, and a decision feedback equalizer. Their interconnections are shown in Figure 2-3. 2.2.5.1 Digital Automatic Gain Control The DAGC scales the echo-free signal to the optimum magnitude for subsequent processing. Its structure is that of an LMS filter, but it is a degenerate case since there is only one tap. A freeze coefficient mode may be specified via the microcomputer interface. This mode disables the coefficient update only. The DAGC gain coefficient can be read or written through the microcomputer interface. Adaptation should be frozen prior to reading or writing the coefficient. N8960DSB 23 2.0 Functional Description 2.2 Receive Section BT8960 Single-Chip 2B1Q Transceiver 2.2.5.2 Feed Forward Equalizer (FFE) The Feed Forward Equalizer (FFE) removes precursors from the received signal. The FFE may be operated in a special adapt last mode. In this mode, which is useful during startup, only the last coefficient is updated. The last coefficient is the one which is multiplied with the oldest data sample, (sample #7). A freeze coefficient mode may be specified via the microcomputer interface. This mode disables the coefficient updates only. A special mode exists to zero all of the coefficients. It is also enabled through the microcomputer interface. Individual FFE coefficients can be read and written through the microcomputer interface. Adaptation should be frozen prior to reading or writing coefficients. The Error Predictor (EP) improves the performance of the equalizer by prognosticating errors before they occur. A freeze coefficient mode may be specified via the microcomputer interface. This mode disables the coefficient updates only. A special mode exists to zero all of the coefficients; it is also enabled through the microcomputer interface. Individual EP coefficients can be read and written through the microcomputer interface. Adaptation should be frozen prior to reading or writing coefficients. The Decision Feedback Equalizer (DFE) removes postcursors from the received signal. A freeze coefficient mode may be specified via the microcomputer interface. This mode disables the coefficient updates only. A zero coefficients mode exists to zero all of the coefficients; it is also enabled through the microcomputer interface. A zero filter output mode exists to zero the output of the FIR with no effect on the coefficients. It is also enabled through the microcomputer interface. Individual DFE coefficients can be read and written through the microcomputer interface. Adaptation should be frozen prior to reading or writing coefficients. The DAGC, FFE, and EP filters are implemented using an internal microprogrammable Digital Signal Processor (DSP) optimized for LMS filters. Internal DSP micro-instructions are stored in an on-chip RAM. This microcode RAM is loaded after powerup through the microcomputer interface when the transceiver is initialized. 2.2.5.3 Error Predictor (EP) 2.2.5.4 Decision Feedback Equalizer (DFE) 2.2.5.5 Microcoding 2.2.6 Detector The detector converts the equalized received signal into a 2B1Q symbol and produces two error signals used in adapting the receiver equalizers. The signal detection uses two sub-blocks, a slicer, and a peak detector. Additionally, the detector contains a scrambler and Bit Error Rate (BER) meter for use during the startup sequence. 2.2.6.1 Slicer The slicer thresholds the equalized signal to produce a 2B1Q symbol. The input to the slicer is the FFE output minus the DFE and EP outputs. The slicer can operate in two modes: two-level and four-level. In the two-level mode, used during the part of startup when the only transmitted symbols are +3 or -3, the slicer threshold is set at zero. When in four-level mode, the cursor level is specified via the microcomputer interface. It is a 16-bit, 2's complement number, but must be positive and less than 0x2AAA for proper operation. 24 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 2.0 Functional Description 2.2 Receive Section 2.2.6.2 Peak Detector (PKD) The PKD is only used during the two-level transmission part of startup. It operates on the echo-free signal. A signal is detected to be a +3, if it is higher than both of its neighbors, or a -3, if it is lower than both of its neighbors. If neither of the peaked conditions exists, the output of the slicer is used. The detector computes two error signals for use in the equalizer: a 16-bit slicer and a 16-bit equalizer. The scrambler may operate as either a scrambler or as a descrambler. The scrambler block is used during the scrambled-ones part of the startup sequence. This provides an error-free signal for equalizer adaptation. This scrambler is essentially a 23-bit-long LFSR with feedback. The feedback point depends on whether the transceiver is being used in a central-office or remote-terminal application. When operating as a descrambler, the input source is the detector output. The symbol is converted to a bit stream, as shown in Table 2-4 for the two-level case. Table 2-4. Two-Level Symbol-to-Bit Conversion Input Symbol -3 +3 2.2.6.3 Error Signals 2.2.6.4 Scrambler Module Output Bit 0 1 The symbol is converted to a bit stream, as shown in Table 2-5 for the fourlevel case. Table 2-5. Four-Level Symbol-to-Bit Conversion Input Symbol -3 -1 +1 +3 First Output Bit (sign) 0 0 1 1 Second Output Bit (magnitude) 0 1 1 0 N8960DSB 25 2.0 Functional Description 2.2 Receive Section BT8960 Single-Chip 2B1Q Transceiver The LFSR operates in the same way in both cases, except in the two-level case it is clocked once-per-symbol and in the four-level case it is clocked twice-persymbol. When operating as a scrambler, the LFSR must first be locked to the far-end source. Once locked, it is then able to replicate the far-end input sequence, when its input is held at all ones. The locking sequence is controlled internally, initiated through the microcomputer interface by setting the lfsr_lock bit of the detector_modes register. The locking sequence consists of the following four steps: 1. Operate the LFSR as a descrambler for 23 bits. 2. Operate the LFSR as a scrambler for 127 bits. The sync detector is active during this period. 3. Go to Step 1 if synchronization was not achieved, otherwise continue to Step 4. 4. Send an interrupt to the microcomputer, if unmasked, indicating successful locking and continue operating as a scrambler. The sequence continues until the lfsr_lock control bit is cleared by the microcomputer. 2.2.6.5 Sync Detector The sync detector compares the output of the scrambler with the output of the symbol detector. The number of equivalent bits is accumulated for 128 comparisons. The result is then compared to a Scrambler Synchronization Threshold Register [scr_sync_th; 0x2E], lock is declared, and the sync bit of the irq_source register is set if the count is greater than the threshold. For a count less than or equal to the threshold, no lock condition is declared and the sync bit is unaffected. The detector consists of five meters: a BER meter, a symbol histogrammer, a noise-level meter, a noise-level histogram meter, and an SNR alarm meter. The BER meter provides an estimate of the bit error rate when the received symbols are known to be scrambled ones. When the LFSR is operating as a descrambler the meter counts the number of ones on the descrambler output. When the LFSR is operating as a scrambler, the BER meter counts the number of equal scrambler, and symbol detector outputs. The counter operates over the meter timer interval [meter_low, meter_high; 0x18, 0x19]. The counter is saturated to 16 bits. At the end of the measurement interval the counter is loaded into the Bit Error Rate Meter Registers [ber_meter_low, ber_meter_high; 0x4C, 0x40]. The symbol histogrammer computes a coarse histogram of the received symbols. It operates by counting the number of ones received during meter timer interval [meter_low, meter_high; 0x18, 0x19]. That is, at the start of the measurement interval a counter is cleared. For each detector output which is +1 or -1, the counter is incremented. If the detector output is +3 or -3, the count is held at its previous value. The count is saturated to 16 bits. At the end of the measurement interval, the 8 MSBs of the counter are loaded into the Symbol Histogram Meter Register [symbol_histogram; 0x4E]. The noise level meter estimates the noise at the input to the slicer. It operates by accumulating the absolute value of the slicer error over meter timer interval [meter_low, meter_high; 0x18, 0x19]. At the end of the measurement interval, the 16 MSBs of the 32-bit accumulator are loaded into the Noise Level Histogram Meter Register [nlm_low, nlm_high; 0x50, 0x51]. 2.2.6.6 Detector Meters 26 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 2.0 Functional Description 2.2 Receive Section The SNR alarm provides a rapid indication of impulse noise disturbances and loss of signal so that corrective action can be taken. The alarm is based on a second noise level meter. The meter is the same as the preceding noise level meter except it operates on a dedicated SNR alarm timer. The absolute value of the slicer error is accumulated during the timer period. At the end of the measurement interval, the 16 MSBs of the accumulator are compared against the SNR Alarm Threshold Register [snr_alarm_th_low, snr_alarm_th_high; 0x34, 0x35]. If the result is greater than this threshold, an interrupt is set in the irq_source register. The threshold is set via the microcomputer interface. N8960DSB 27 2.0 Functional Description 2.3 Timing Recovery and Clock Interface BT8960 Single-Chip 2B1Q Transceiver 2.3 Timing Recovery and Clock Interface The timing recovery and clock interface block diagram consists of the timing recovery circuit and the crystal amplifier, as detailed in Figure 2-5. The main purpose of this circuitry is to recover the clock from the received data. Control fields include the hclk_freq[1,0] bits of the Serial Monitor Source Select Register [serial_monitor_source; 0x01], the PLL Modes Register [pll_modes; 0x22], the Timing Recovery PLL Phase Offset Register [pll_phase_offsset_low, pll_phase_offset_high; 0x24, 0x25] and the PLL Frequency Register [pll_frequency_low, pll_frequency_high; 0x5E, 0x5F]. See the Register section of this datasheet for descriptions of these control fields. Figure 2-5. Timing Recovery and Clock Interface Block Diagram Phase Detector Meter Register [0x40, 0x41] Control Registers Detected Symbol Equalizer Error Timing Recovery Circuit QCLK (87) HCLK (35) XOUT (36) Crystal Amplifier XTALI (40) XTALO (39) Y1 C10 C11 Digital Ground 28 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 2.0 Functional Description 2.3 Timing Recovery and Clock Interface 2.3.0.7 Timing Recovery Circuit The timing recovery circuit uses the BT8960's internal detected symbol and equalizer error signals to regenerate the received data symbol clock (QCLK). The HCLK output is synchronized with the edges of the symbol clock (QCLK), unlike the XOUT output which is a buffered output of the crystal amplifier. HCLK can be programmed for rates of 16, 32, or 64 times the symbol rate. The timing recovery circuit includes a phase detector meter that measures the average value of the phase correction signal. This information can be used during startup to set the phase offset in the Receive Phase Select Register [receive_phase_select; 0x07]. The output of the phase detector is accumulated over the meter timer interval [meter_low, meter_high; 0x18, 0x19]. At the end of the measurement interval, the value is loaded into the Phase Detector Meter Register [pdm_low, pdm_high; 0x40, 0x41]. The user can also bypass the timing recovery circuit and directly specify the frequency via the PLL Frequency Register [pll_frequency_low, pll_frequency_high; 0x5E, 0x5F]. The crystal amplifier reduces the support circuitry needed for the BT8960 by eliminating the need for an external Voltage-Controlled Crystal Oscillator (VCXO) or a Crystal Oscillator (XO). A crystal can be connected directly to the XTALI and XTALO pins. Table 2-6 gives the recommended component values for this circuit. The crystal amplifier can also accommodate an external clock input by connecting the external clock to the XTALI input pin. Table 2-6. Crystal Oscillator Circuit Component Values Component Y1 2.3.0.8 Crystal Amplifier Value 32 times the data rate N8960DSB 29 2.0 Functional Description 2.4 Channel Unit Interface BT8960 Single-Chip 2B1Q Transceiver 2.4 Channel Unit Interface The quaternary signals of the channel unit interface have four modes which are programmable through bits 0 and 1 of the Channel Unit Interface Modes Register [cu_interface_modes; 0x06]. They are: serial sign-bit first, serial magnitude-bit first, parallel master, and parallel slave. In serial mode, a Bit Rate Clock (BCLK) is output at twice the symbol rate. The sign and magnitude bits of the receive data are output through RDAT on the rising edge of BCLK. The sign and magnitude bits of the transmit data are sampled on the falling edge of BCLK at the TDAT input. The sign bit is transferred first, followed by the magnitude bit of a given symbol in sign-bit first mode, while the opposite occurs in magnitude-bit first mode. The clock relationships for serial sign-bit first mode are illustrated in Figure 2-6. Figure 2-6. Serial Sign-Bit First Mode BCLK Bit-Rate Clock QCLK RDAT Sign0 Magnitude0 Sign1 Magnitude1 Sign2 TDAT Sign0 Magnitude0 Sign1 Magnitude1 Sign2 In parallel master mode, the sign and magnitude receive data is output through RQ[1] and RQ[0], respectively, on the rising edge of QCLK. The quaternary transmit data is sampled on the falling edge of QCLK. This clock and data relationship is illustrated in Figure 2-7. Figure 2-7. Parallel Master Mode QCLK RQ[1]/TQ[1] Sign0 Sign1 Sign2 RQ[0]/TQ[0] Magnitude0 Magnitude1 Magnitude2 30 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 2.0 Functional Description 2.4 Channel Unit Interface Parallel slave mode uses RBCLK and TBCLK inputs to synchronize data transfer. RBCLK and TBCLK must be frequency-locked to QCLK, though the use of two internal FIFOs allow an arbitrary phase relationship to QCLK. TQ[1] and TQ[0] are sampled on the active edge of TBCLK, as programmed through the MCI. RQ[1] and RQ[0] are output on the active edge of RBCLK, also as programmed through the MCI. The clock relationships for the case where TBCLK is programmed to be falling-edge active and RBCLK is rising-edge active are illustrated in Figure 2-8. Figure 2-8. Parallel Slave Mode TBCLK TQ[1] Sign0 Sign1 Sign2 TQ[0] Magnitude0 Magnitude1 Magnitude2 RBCLK RQ[1] Sign0 Sign1 Sign2 RQ[0] Magnitude0 Magnitude1 Magnitude2 N8960DSB 31 2.0 Functional Description 2.5 Microcomputer Interface BT8960 Single-Chip 2B1Q Transceiver 2.5 Microcomputer Interface The microcomputer interface provides operational mode control and status through internal registers. A microcomputer write sets the operating modes to the appropriate registers. A read to a register verifies the operating mode or provides the status. The microcomputer interface can be programmed to generate an interrupt on certain conditions. 2.5.1 Source Code Rockwell provides portable C-source code under a no-cost licensing agreement. This source code provides a startup procedure, as well as diagnostic and system monitoring functions. 2.5.2 Microcomputer Read/Write The microcomputer interface uses either an 8-bit-wide multiplexed address-data bus (Intel-style), or an 8-bit-wide data bus and another separate 8-bit-wide address bus (Motorola-style) for external data communications. The interface provides access to the internal control and status registers, coefficients, and microcode RAM. The interface is compatible with Intel or Motorola microcomputers, and is configured with the inputs, MOTEL and MUXED. MOTEL low selects Intel-type microcomputer and control signals: ALE, CS, RD, and WR. MOTEL high selects Motorola-type microcomputer and control signals: ALE, CS, DS, and R/W. MUXED high configures the interface to use the multiplexed address-data bus with both the address and data on the AD[7:0] pins. MUXED low configures the interface to use separate address and data bused with the data on the AD[7:0] pins and the address on the ADDR[7:0] pins. The READY pin is provided to indicate when the BT8960 is ready to transfer data and can be used by the microcomputer to insert wait states in read or write cycle. The microcomputer interface provides access to a 256-byte internal address space. These registers provide configuration, control, status, and monitoring capabilities. Meter values are read lower-byte then upper-byte. When the lower-byte is read, the upper-byte is latched at the corresponding value. This ensures that multiple byte values correspond to the same reading. Most information can be directly read or written; however, the filter coefficients require an indirect access. 32 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 2.0 Functional Description 2.5 Microcomputer Interface 2.5.2.1 RAM Access Registers The internal RAMs of the transmit filter, LEC, NEC, DFE, equalizer, and microcode are accessed indirectly. They all share a common data register which is used for both read and write operations: Access Data Register [access_data_byte[3:0]; [0x7C-0x7F]. Each RAM has an individual read select and write select register. These registers specify the location to access and trigger the actual RAM read or write. To perform a read, the address of the desired RAM location is first written to the corresponding read tap select register. Two symbol periods afterwards, the individual bytes of that location are available for reading from the Access Data Register. To perform a write, the value to be written is first stored in the Access Data Register. The address of the affected RAM location is then written to the corresponding write tap select register. When writing the same value to multiple locations, it is not necessary to rewrite the Access Data Register. To assure reliable access to the embedded RAMs, internal read and write operations are performed synchronous to the symbol clock. This has the effect of limiting access to these internal RAMs to one every other cycle. When reading or writing multiple filter coefficients, it may be desirable to freeze adaptation so that all values will correspond to the same state. The timing for a read or write cycle is stated explicitly in the Electrical and Mechanical Specifications section. During a read operation, an external microcomputer places an address on the address-data bus which is then latched on the falling edge of ALE. Data is placed on the address-data bus after CS, RD, or DS go low. The read cycle is completed with the rising edge of CS, RD, or DS. A write operation latches the address from the address-data bus at the falling edge of ALE. The microcomputer places data on the address-data bus after CS, WR, or DS go low. Motorola MCI will have R/W falling edge preceding the falling edge of CS and DS. The rising edge of R/W will occur after the rising edge of CS and DS. Data is latched on the address-data bus on the rising edge of WR or DS. The timing for a read or write cycle using the separated address and data buses is essentially the same as over the multiplexed bus. The one exception is that the address must be driven onto the ADDR[7:0] bus rather than the AD[7:0] bus. 2.5.2.2 Multiplexed Address/Data Bus 2.5.2.3 Separated Address/ Data Bus 2.5.3 Interrupt Request The twelve interrupt sources consist of: eight timers, a far-end signal high alarm, a far-end signal low alarm, a SNR alarm, and a scrambler synchronization detection. All of the interrupts are requested on a common pin, IRQ. Each interrupt may be individually enabled or disabled through the Interrupt Mask Registers [mask_low_reg, mask_high_reg; 0x02, 0x03]. The cause of an interrupt is determined by reading the Timer Source Register [timer_source; 0x04] and the IRQ Source Register [irq_source; 0x05]. The timer interrupt status is set only when the timer transitions to zero. Alarm interrupts cannot be cleared while the alarm is active. In other words, it cannot be cleared while the condition still exists. IRQ is an open-drain output and must be tied to a pull-up resistor. This allows IRQ to be tied together with a common interrupt request. N8960DSB 33 2.0 Functional Description 2.5 Microcomputer Interface BT8960 Single-Chip 2B1Q Transceiver 2.5.4 Reset The reset input (RST) is an active-low input that places the transceiver in an inactive state by setting the mode bit (0) in the Global Modes and Status Register [global_modes; 0x00]. An internal supply monitor circuit ensures that the transceiver will be in an inactive state upon initial application of power to the chip. 2.5.5 Registers The BT8960 has many directly addressable registers. These registers include control and monitoring functions. Write operations to undefined registers will have unpredictable effects. Read operations from undefined registers will have undefined results. 2.5.6 Timers Eight timers are integrated into the BT8960 to control the various on-chip meters and to aid the microcomputer in stepping through the events of the startup sequence. The structure of each timer includes down counter, zero detect logic, and control circuitry, which determines when the counter is reloaded or decremented. For each of the eight timers, there is a 2-byte timer interval register that determines the value from which the timer decrements. There are three 8-bit registers: the Timer Restart Register [timer_restart; 0x0C], the Timer Enable Register [timer_enable; 0x0D], and the Timer Continuous Mode Register [timer_continuous; 0x0E]. These registers control the operation of the timers. Each bit of the 8-bit registers corresponds to a timer. Each logic-high bit in timer_restart acts as an event that causes the corresponding timer to reload. Each logic-high bit in timer_enable acts to enable the corresponding timer. Each logic-high bit in timer_continuous acts to reload the counter after timing out. Each counter is loaded with the value in its interval register. The counter decrements until it reaches zero. Upon reaching zero, an interrupt is generated if enabled by the Interrupt Mask Low Register [mask_low_reg, mask_high_reg; 0x02, 0x03]. The interrupt is edge-triggered so that only one interrupt will be caused by a single time out. 34 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 2.0 Functional Description 2.5 Microcomputer Interface A prescaler may precede the timer. This increases the time span available at the expense of resolution. Only the startup timers have prescalers. Table 2-7 provides summary information on the timers. Table 2-7. Timers Timer Name Startup Timer 1 Startup Timer 2 Startup Timer 3 Startup Timer 4 SNR Alarm Timer Meter Timer General Purpose Timer 3 General Purpose Timer 4 Purpose Startup Events Startup Events Startup Events Startup Events SNR Measurement Measurement Miscellaneous Miscellaneous Clock Rate Symbol rate / 1024 Symbol rate / 1024 Symbol rate / 1024 Symbol rate / 1024 Symbol rate Symbol rate Symbol rate Symbol rate Control Bits sut 1 sut 2 sut 3 sut 4 snr meter t3 t4 Four timers are provided for use in timing startup events. These timers share a single prescaler which divides the symbol clock by 1,024 and supplies this slow clock to the four counters. The timers are: Startup Timer 1, Startup Timer 2, Startup Timer 3, and Startup Timer 4. Each one is independent, with separate interval timer values and interrupts. Two timers control the measurement intervals for the various meters: the SNR Alarm Timer and the Meter Timer. The SNR Alarm Timer is used only by the low SNR, while the Meter Timer is used by all other meters, excluding the low SNR meter. Their respective interrupts for each timer signal are set when they expire. There are no prescalers for these timers; they count at the symbol rate. Both timers are normally used in the continuous mode. Two timers are provided for general use: General Purpose Timer 3 and General Purpose Timer 4. Both timers are identical. There are no prescalers for these timers; they count at the symbol rate. Each timer signals an interrupt when it expires. N8960DSB 35 2.0 Functional Description 2.6 Test and Diagnostic Interface (JTAG) BT8960 Single-Chip 2B1Q Transceiver 2.6 Test and Diagnostic Interface (JTAG) As the complexity of communications chips increases, the need to easily access individual chips for PCB verification is becoming vital. As a result, special circuitry has been incorporated within the transceiver which complies fully with IEEE standard 1149.1-1990, "Standard Test Access Port and Boundary Scan Architecture" set by the Joint Test Action Group. JTAG has four dedicated pins that comprise the Test Access Port (TAP): Test Mode Select (TMS), Test Clock (TCK), Test Data Input (TDI), and Test Data Out (TDO). Verification of the integrated circuit and its connection to other modules on the printed circuit board can be achieved through these four TAP pins. JTAG's approach to testability utilizes boundary scan cells placed at each digital pin, both inputs and outputs. All scan cells are interconnected into a boundary-scan register which applies or captures test data used for functional verification of the PC board interconnection. JTAG is particularly useful for board testers using functional testing methods. With boundary-scan cells at each digital pin, the ability to apply and capture the respective logic levels is provided. Since all of the digital pins are interconnected as a long shift register, the TAP logic has access and control of all necessary pins to verify functionality. For mixed signal ICs, the chip boundary definition is expanded to include the on-chip interface between digital and analog circuitry. Internal supply monitor circuitry ensures that each pin is initialized to operate as an 2B1Q transceiver, instead of JTAG test mode during a power-up sequence. The JTAG standard defines an optional device identification register. This register is included and contains a revision number, a part number, and a manufacturers identification code specific to Rockwell. Access to this register is through the TAP controller via the standard JTAG instruction set (see Table 2-8). A variety of verification procedures can be performed through the TAP controller. Board connectivity can be verified at all digital pins through a set of four instructions accessible through the use of a state machine standard to all JTAG controllers. Refer to the IEEE 1149.1 specification for details concerning the Instruction Register and JTAG state machine. A Boundry Scan Description Language (BSDL) file for the BT8960 is also available from the factory upon request. Table 2-8. JTAG Device Identification Register Version(1) 0 0 0x0 4 bits 0 0 0 0 1 0 0 0 Part Number 1 1 0 0 0 0 0 0 0 0 0 0 0 1 Manufacturer ID 1 0 1 0 1 1 0 1 0x2300 16 bits 0x0D6 11 bits TDO Notes: (1). Consult factory for current version number. 36 N8960DSB 3.0 Registers 3.1 Conventions Unless otherwise noted, the following conventions apply to all applicable register descriptions: * For storage of multiple-bit data fields within a single byte-wide register, the Least Significant Bits (LSBs) of the field are located at the lower register-bit positions, while the Most Significant Bits (MSBs) are located at the higher positions. * If only a single data field is stored in a byte-wide register, the field will be justified such that the LSB of the field is located in the lowest register-bit position, bit 0. * For storage of multiple-byte data words across multiple byte-wide registers, the least significant bytes of the word are located at the lower byte-address locations, while the most significant bytes are located at the higher byte-address locations. * When writing to any control or data register with less than all 8-bit positions defined, a logic zero value must be assigned to each unused/undefined/reserved position. Writing a logic one value to any of these positions may cause undefined behavior. * When reading from any control/status or data register with less than all 8-bit positions defined, an indeterminate value will be returned from each unused/undefined/reserved position. * Register values are not affected by RST pin assertion, except for the mode bit of the Global Modes and Status Register [global_modes; 0x00], the hclk_freq[1,0] field of the Serial Monitor Source Select Register [serial_monitor_source; 0x01] and the clk_freq[1,0] field of the PLL Modes Register [pll_modes; 0x22]. Upon RST pin assertion, all RAM is lost except for the equalizer microcode and scratch pad RAM. * The initial values of all registers and RAM are undefined after power is applied. Exceptions include the mode bit of the Global Modes and Status Register, the hclk_freq[1,0] field of the Serial Monitor Source Select Register and the clk_freq[1,0] field of the PLL Modes Register. In addition, the JTAG state is reset when power is applied. * The register and bit mnemonics used here are based on the mnemonics used in the Rockwell bit pump software. N8960DSB 37 3.2 Register Summary Table 3-1. Register Table (1 of 6) ADDR (hex) Register Label Read Write Bit Number 7 hw_revision[ 3] hclk_freq[1] t4 -- t4 -- -- -- -- negate_symb ol -- 38 N8960DSB Register Summary Registers 6 hw_revision[2] hclk_freq[0] t3 -- t3 -- -- -- -- symbol_ delay[2] -- isolated_ pulse[1] t3 t3 t3 5 hw_revision[1] smon[5] snr -- snr -- -- -- enable_dc_tap symbol_ delay[1] -- isolated_ pulse[0] snr snr snr 4 hw_revision[0] smon[4] meter -- meter -- tbclk_pol -- adapt_coefficien ts symbol_delay[0] 3 part_id[2] smon[3] sut4 sync sut4 sync rbclk_pol rphs[3] zero_coefficients adapt_ coefficients adapt_ coefficients htur_lfsr sut4 sut4 sut4 2 part_id[1] smon[2] sut3 high_felm sut3 high_felm fifos_mode rphs[2] zero_output zero_ coefficients zero_ coefficients data_source[2] sut3 sut3 sut3 1 part_id[0] smon[1] sut2 low_felm sut2 low_felm interface_ mode1 rphs[1] adapt_gain[1] 0 mode smon[0] sut1 low_snr sut1 low_snr interface_ mode[0] rphs[0] adapt_gain[0] 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 global_modes serial_monitor_source mask_low_reg mask_high_reg timer_source irq_source cu_interface_modes receive_phase_select linear_ec_modes R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x09 nonlinear_ec_modes R/W zero_output adapt_gain Single-Chip 2B1Q Transceiver 0x0A dfe_modes R/W -- zero_output adapt_gain 0x0B 0x0C 0x0D 0x0E transmitter_modes timer_restart timer_enable timer_continuous R/W R/W R/W R/W -- t4 t4 t4 transmitter_off meter meter meter data_source[1] sut2 sut2 sut2 data_source[0] sut1 sut1 sut1 BT8960 Single-Chip 2B1Q Transceiver BT8960 Table 3-1. Register Table (2 of 6) ADDR (hex) 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x20 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x21 0x22 Register Label reserved2 sut1_low sut1_high sut2_low sut2_high sut3_low sut3_high sut4_low sut4_high meter_low meter_high reserved9 snr_timer_low snr_timer_high t3_low t3_high t4_low t4_high adc_control pll_modes Read Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Number 7 D[7] D[7] D[15] D[7] D[15] D[7] D[15] D[7] D[15] D[7] D[15] D[7] D[7] D[15] D[7] D[15] D[7] D[15] -- clk_freq[1] 6 D[6] D[6] D[14] D[6] D[14] D[6] D[14] D[6] D[14] D[6] D[14] D[6] D[6] D[14] D[6] D[14] D[6] D[14] -- clk_freq[0] 5 D[5] D[5] D[13] D[5] D[13] D[5] D[13] D[5] D[13] D[5] D[13] D[5] D[5] D[13] D[5] D[13] D[5] D[13] loop_back[1] -- 4 D[4] D[4] D[12] D[4] D[12] D[4] D[12] D[4] D[12] D[4] D[12] D[4] D[4] D[12] D[4] D[12] D[4] D[12] loop_back[0] phase_detector_ gain[1] 3 D[3] D[3] D[11] D[3] D[11] D[3] D[11] D[3] D[11] D[3] D[11] D[3] D[3] D[11] D[3] D[11] D[3] D[11] -- phase_detector_ gain[0] 2 D[2] D[2] D[10] D[2] D[10] D[2] D[10] D[2] D[10] D[2] D[10] D[2] D[2] D[10] D[2] D[10] D[2] D[10] gain[2] freeze_pll 1 D[1] D[1] D[9] D[1] D[9] D[1] D[9] D[1] D[9] D[1] D[9] D[1] D[1] D[9] D[1] D[9] D[1] D[9] gain[1] pll_gain[1] 0 D[0] D[0] D[8] D[0] D[8] D[0] D[8] D[0] D[8] D[0] D[8] D[0] D[0] D[8] D[0] D[8] D[0] N8960DSB Register Summary D[8] gain[0] pll_gain[0] Registers 39 Table 3-1. Register Table (3 of 6) ADDR (hex) 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 40 N8960DSB Register Summary Registers Register Label reserved10 pll_phase_offset_low pll_phase_offset_high dc_offset_low dc_offset_high tx_calibrate tx_gain noise_histogram_th_low noise_histogram_th_high ep_pause_th_low ep_pause_th_high scr_sync_th far_end_high_alarm_th_low far_end_high_alarm_th_high far_end_low_alarm_th_low far_end_low_alarm_th_high snr_alarm_th_low snr_alarm_th_high cursor_level_low cursor_level_high Read Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Number 7 D[7] D[7] D[15] D[7] D[15] -- -- D[7] D[15] D[7] D[15] D[7] D[7] D[15] D[7] D[15] D[7] D[15] D[7] D[15] 6 D[6] D[6] D[14] D[6] D[14] -- -- D[6] D[14] D[6] D[14] D[6] D[6] D[14] D[6] D[14] D[6] D[14] D[6] D[14] 5 D[5] D[5] D[13] D[5] D[13] tx_calibrate[3] tx_gain[3] D[5] D[13] D[5] D[13] D[5] D[5] D[13] D[5] D[13] D[5] D[13] D[5] D[13] 4 D[4] D[4] D[12] D[4] D[12] tx_calibrate[2] tx_gain[2] D[4] D[12] D[4] D[12] D[4] D[4] D[12] D[4] D[12] D[4] D[12] D[4] D[12] 3 D[3] D[3] D[11] D[3] D[11] tx_calibrate[1] tx_gain[1] D[3] D[11] D[3] D[11] D[3] D[3] D[11] D[3] D[11] D[3] D[11] D[3] D[11] 2 D[2] D[2] D[10] D[2] D[10] tx_calibrate[0] tx_gain[0] D[2] D[10] D[2] D[10] D[2] D[2] D[10] D[2] D[10] D[2] D[10] D[2] D[10] 1 D[1] D[1] D[9] D[1] D[9] -- -- D[1] D[9] D[1] D[9] D[1] D[1] D[9] D[1] D[9] D[1] D[9] D[1] D[9] 0 D[0] D[0] D[8] D[0] D[8] -- -- D[0] D[8] D[0] D[8] D[0] D[0] D[8] Single-Chip 2B1Q Transceiver D[0] D[8] D[0] D[8] D[0] D[8] BT8960 Single-Chip 2B1Q Transceiver BT8960 Table 3-1. Register Table (4 of 6) ADDR (hex) 0x38 0x39 0x3A 0x3B 0x3C Register Label dagc_target_low dagc_target_high detector_modes peak_detector_delay dagc_modes Read Write R/W R/W R/W R/W R/W Bit Number 7 D[7] D[15] enable_peak_ detector -- -- 6 D[6] D[14] output_mux_ control[1] -- -- 5 D[5] D[13] output_mux_ control[0] -- -- 4 D[4] D[12] scr_out_to_dfe -- -- 3 D[3] D[11] two_level D[3] -- 2 D[2] D[10] lfsr_lock D[2] eq_error_ adaption zero_ coefficients zero_ coefficients D[12] D[20] D[2] D[18] D[26] D[18] D[26] D[18] D[26] D[2] D[10] 1 D[1] D[9] htur_lfsr D[1] adapt_ coefficient adapt_ coefficient adapt_ coefficients D[11] D[19] D[1] D[17] D[25] D[17] D[25] D[17] D[25] D[1] D[9] 0 D[0] D[8] descr_on D[0] adapt_gain 0x3D ffe_modes R/W -- -- -- -- adapt_last_coeff adapt_gain N8960DSB 0x3E 0x40 0x41 0x42 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B ep_modes pdm_low pdm_high overflow_meter dc_meter_low dc_meter_high slm_low slm_high felm_low felm_high noise_histogram_low noise_histogram_high R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- D[17] D[25] D[7] D[23] D[31] D[23] D[31] D[23] D[31] D[7] D[15] -- D[16] D[24] D[6] D[22] D[30] D[22] D[30] D[22] D[30] D[6] D[14] -- D[15] D[23] D[5] D[21] D[29] D[21] D[29] D[21] D[29] D[5] D[13] -- D[14] D[22] D[4] D[20] D[28] D[20] D[28] D[20] D[28] D[4] D[12] zero_output D[13] D[21] D[3] D[19] D[27] D[19] D[27] D[19] D[27] D[3] D[11] adapt_gain D[10] D[18] D[0] D[16] D[24] D[16] D[24] D[16] Register Summary D[24] D[0] D[8] Registers 41 Table 3-1. Register Table (5 of 6) ADDR (hex) 0x4C 0x4D 0x4E 0x50 0x51 0x5E 0x5F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 42 N8960DSB Register Summary Registers Register Label ber_meter_low ber_meter_high symbol_histogram nlm_low nlm_high pll_frequency_low pll_frequency_high linear_ec_tap_select_read linear_ec_tap_select_write nonlinear_ec_tap_select_read nonlinear_ec_tap_select_write dfe_tap_select_read dfe_tap_select_write sp_tap_select_read sp_tap_select_write eq_add_read eq_add_write Read Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Number 7 D[7] D[15] D[7] D[23] D[31] D[22] D[30] -- -- -- -- -- -- -- -- -- -- 6 D[6] D[14] D[6] D[22] D[30] D[21] D[29] -- -- -- -- -- -- -- -- -- -- 5 D[5] D[13] D[5] D[21] D[29] D[20] D[28] D[5] D[5] D[5] D[5] D[5] D[5] D[5] D[5] D[5] D[5] 4 D[4] D[12] D[4] D[20] D[28] D[19] D[27] D[4] D[4] D[4] D[4] D[4] D[4] D[4] D[4] D[4] D[4] 3 D[3] D[11] D[3] D[19] D[27] D[18] D[26] D[3] D[3] D[3] D[3] D[3] D[3] D[3] D[3] D[3] D[3] 2 D[2] D[10] D[2] D[18] D[26] D[17] D[25] D[2] D[2] D[2] D[2] D[2] D[2] D[2] D[2] D[2] D[2] 1 D[1] D[9] D[1] D[17] D[25] D[16] D[24] D[1] D[1] D[1] D[1] D[1] D[1] D[1] D[1] D[1] D[1] 0 D[0] D[8] D[0] D[16] D[24] D[15] D[23] D[0] D[0] D[0] D[0] D[0] D[0] D[0] Single-Chip 2B1Q Transceiver D[0] D[0] D[0] BT8960 Single-Chip 2B1Q Transceiver BT8960 Table 3-1. Register Table (6 of 6) ADDR (hex) 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F Register Label eq_microcode_add_read eq_microcode_add_write access_data_byte0 access_data_byte1 access_data_byte2 access_data_byte3 Read Write R/W R/W R/W R/W R/W R/W Bit Number 7 -- -- D[7] D[15] D[23] D[31] 6 -- -- D[6] D[14] D[22] D[30] 5 D[5] D[5] D[5] D[13] D[21] D[29] 4 D[4] D[4] D[4] D[12] D[20] D[28] 3 D[3] D[3] D[3] D[11] D[19] D[27] 2 D[2] D[2] D[2] D[10] D[18] D[26] 1 D[1] D[1] D[1] D[9] D[17] D[25] 0 D[0] D[0] D[0] D[8] D[16] D[24] N8960DSB Register Summary Registers 43 3.0 Registers 3.1 Conventions BT8960 Single-Chip 2B1Q Transceiver 3.2.1 0x00--Global Modes and Status Register (global_modes) 7 hw_revision[3] 6 hw_revision[2] 5 hw_revision[1] 4 hw_revision[0] 3 part_id[2] 2 part_id[1] 1 part_id[0] 0 mode hw_revision[3:0] Chip Revision Number--Read-only unsigned binary field encoded with the chip revision number. Smaller values represent earlier versions while larger values represent later versions. The zero value represents the original prototype release. Consult factory for current value and revision. Part ID--Read-only binary field set to binary 001 identifying the part as BT8960. Power Down Mode--Read/write control bit. When set, stops all filter processing and zeros the transmit output for reduced power consumption. All RAM contents are preserved. The mode bit is automatically set by RST assertion and upon initial power application. It can be cleared only by writing a logic zero, at which time filter processing and transmitter operation can proceed. part_id[2:0] mode 3.2.2 0x01--Serial Monitor Source Select Register (serial_monitor_source) 7 hclk_freq[1] 6 hclk_freq[0] 5 smon[5] 4 smon[4] 3 smon[3] 2 smon[2] 1 smon[1] 0 smon[0] hclk_freq[1,0] HCLK Frequency Select--Read/write binary field selects the frequency of the HCLK output. hclk_freq[1] 0 0 1 1 hclk_freq[0] 0 1 0 1 HCLK Frequency Symbol Frequency (FQCLK) times 64 hclk_freq[1,0] is set to "00" upon assertion of the RST pin and power-on detection. Symbol Frequency (FQCLK) times 16 Symbol Frequency (FQCLK) times 32 Symbol Frequency (FQCLK) times 64 44 N8960DSB BT8960 Single-Chip 2B1Q Transceiver smon[5:0] 3.0 Registers 3.1 Conventions Serial Monitor Source Select--Read/write binary field selects the Serial Monitor (SMON) output source. smon[5:0] Source Decimal 0 - 47 48 49 50 51 52 53 Binary 00 0000 - 10 1111 11 0000 11 0001 11 0010 11 0011 11 0100 11 0101 Equalizer Register File Digital Front-End Output/LEC Input Linear Echo Replica DFE Subtactor Output/EP Input EP Subtractor Output/Slicer Input Timing Recovery Phase Detector Output/Loop Filter Input Timing Recovery Loop Filter Output/Frequency Synthesizer Input 3.2.3 0x02--Interrupt Mask Register Low (mask_low_reg) Independent read/write mask bits for each of the Timer Source Register [timer_source; 0x04] interrupt flags. A logic one represents the masked condition. A logic zero represents the unmasked condition. All mask bits behave identically with respect to their corresponding interrupt flags. Setting a mask bit prevents the corresponding interrupt flag from affecting the IRQ output. Clearing a mask allows the interrupt flag to affect IRQ output. Unmasking an active interrupt flag will immediately cause the IRQ output to go active, if currently inactive. Masking an active interrupt flag will cause IRQ to go inactive, if no other unmasked interrupt flags are set. 7 t4 6 t3 5 snr 4 meter 3 su4 2 sut3 1 sut2 0 sut1 t4 t3 snr meter sut4 sut3 sut2 sut1 General Purpose Timer 4 General Purpose Timer 3 SNR Alarm Timer Meter Timer Startup Timer 4 Startup Timer 3 Startup Timer 2 Startup Timer 1 N8960DSB 45 3.0 Registers 3.1 Conventions BT8960 Single-Chip 2B1Q Transceiver 3.2.4 0x03--Interrupt Mask Register High (mask_high_reg) Independent read/write mask bits for each of the IRQ Source Register [irq_source; 0x05] interrupt flags. Individual mask bit behavior is identical to that specified for Interrupt Mask Register Low [mask_low_reg; 0x02]. 7 - 6 - 5 - 4 - 3 sync 2 high_felm 1 low_felm 0 low_snr sync high_felm low_felm low_snr Sync Indication Far-End Level Meter High Alarm Far-End Level Meter High Alarm Signal-to-Noise Ratio Low Alarm 3.2.5 0x04--Timer Source Register (timer_source) Independent read/write (zero only) interrupt flags, one for each of eight internal timers. Each flag bit is set and stays set when its corresponding timer value transitions from one to zero. If unmasked, this event will cause the IRQ output to be activated. Flags are cleared by writing them with a logic zero value. Once cleared, a steadystate timer value of zero will not cause a flag to be reasserted. Clearing an unmasked flag will cause the IRQ output to return to the inactive state, if no other unmasked interrupt flags are set. 7 t4 6 t3 5 snr 4 meter 3 sut4 2 sut3 1 sut2 0 sut1 t4 t3 snr meter sut4 sut3 sut2 sut1 General Purpose Timer 4 General Purpose Timer 3 SNR Alarm Timer Meter Timer Startup Timer 4 Startup Timer 3 Startup Timer 2 Startup Timer 1 46 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 3.0 Registers 3.1 Conventions 3.2.6 0x05--IRQ Source Register (irq_source) Independent read/write (zero only) interrupt flags, one for each of four internal sources. Each flag bit is set and stays set when its corresponding source indicates that a valid interrupt condition exists. If unmasked, this event will cause the IRQ output to be activated. Writing a logic zero to an interrupt flag whose underlying condition no longer exists will cause the flag to be immediately cleared. Attempting to clear a flag whose underlying condition still exists will not immediately clear the flag, but will allow it to remain set until the underlying condition expires, at which time the flag will be cleared automatically. The clearing of an unmasked flag will cause the IRQ output to return to an inactive state, if no other unmasked interrupt flags are set. 7 - 6 - 5 - 4 - 3 sync 2 high_felm 1 low_felm 0 low_snr sync Sync Indication--Active when the sync detector is enabled and its accumulated equivalent comparisons exceeds (greater than) the threshold value stored in the Scrambler Sync Threshold Register [scr_sync_th; 0x2E]. Far-End Level Meter High Alarm--Active when the far-end level meter value exceeds (greater than) the threshold stored in the Far-End High Alarm Threshold Registers [far_end_high_alarm_th_low, far_end_high_alarm_th_high; 0x30-0x31]. Far-End Level Meter Low Alarm--Active when the far-end level meter value exceeds (less than) the threshold stored in the Far-End Low Alarm Threshold Registers [far_end_low_alarm_th_low, far_end_low_alarm_th_high; 0x32-0x33]. Signal-to-Noise Ratio Low Alarm--Active when the SNR Alarm meter value exceeds (greater than) the threshold stored in the SNR Alarm Threshold Registers [snr_alarm_th_low, snr_alarm_th_high; 0x34-0x35]. high_felm low_felm low_snr 3.2.7 0x06--Channel Unit Interface Modes Register (cu_interface_modes) 7 - 6 - 5 - 4 tbclk_pol 3 rbclk_pol 2 fifos_mode 1 0 interface_mode[1] interface_mode[0] tbclk_pol Transmit Baud Clock Polarity--Read/write control bit defines the polarity of the TBCLK input while in the parallel slave interface mode. When set, TQ[1,0] is sampled on the falling edge of TBCLK; when cleared, TQ[1,0] is sampled on the rising edge. Receive Baud Clock Polarity--Read/write control bit defines the polarity of the RBCLK input while in the parallel slave interface mode. When set, RQ[1,0] is updated on the falling edge of RBCLK; when cleared, RQ[1,0] is updated on the rising edge. FIFO's Mode--Read/write control bit used to stagger the transmit and receive FIFO's read and write pointers while in the parallel slave interface mode. A logic one forces the pointers to a staggered position, while a logic zero allows them to operate normally. Must be first set, then cleared once after QCLK-TBCLK-RBCLK frequency lock is achieved to maximize phaseerror tolerance. Interface Mode--Read/write binary field specifies one of four operating modes for the channel unit interface. N8960DSB rbclk_pol fifos_mode interface_ mode[1,0] 47 3.0 Registers 3.1 Conventions BT8960 Single-Chip 2B1Q Transceiver Interface mode [1:0] 00 01 Pin Functions Mode 91 Parallel Master --Parallel quat transfer synchronized to QCLK out. Parallel Slave--Parallel quat transfer synchronized to separate TBCLK and RBCLK inputs. Serial, Magnitude First. Serial quat transfer synchronized to BCLK out; magnitude-bit first followed by sign bit. Serial, Sign First. Serial quat transfer synchronized to BCLK out; sign-bit first followed by magnitude bit. Not used TBCLK 90 Not used RBCLK 88 RQ[1] RQ[1] 89 RQ[0] RQ[0] 85 TQ[1] TQ[1] 86 TQ[0] TQ[0] 10 Not used Not used Not used Not used RDAT BCLK TDAT Not used Not used 11 RDAT BCLK TDAT 3.2.8 0x07--Receive Phase Select Register (receive_phase_select) 7 - 6 - 5 - 4 - 3 rphs[3] 2 rphs[2] 1 rphs[1] 0 rphs[0] rphs[3:0] Receive Phase Select--Read/write binary field that defines the relative phase relationship between QCLK and the sampling point of the ADC. The rising edges of QCLK corresponds to the ADC sampling point when rphs = 0000. Each binary increment of rphs represents a onesixteenth QCLK period delay in the sampling point relative to QCLK. 3.2.9 0x08--Linear Echo Canceller Modes Register (linear_ec_modes) 7 - 6 - 5 enable_dc_tap 4 adapt_ coefficients 3 zero_coefficients 2 zero_output 1 adapt_gain[1] 0 adapt_gain[0] enable_dc_tap Enable DC Tap--Read/write control bit which, when set, forces a constant +1 value into the last data tap of the Linear Echo Canceller (LEC). This condition enables cancellation of any residual DC offset present at the input to the LEC. When cleared, the last data tap operates normally, as the oldest transmit data sample. Adapt Coefficients--Read/write control bit which enables coefficient adaptation when set; disables/freezes adaptation when cleared. Coefficient values are preserved when adaptation is disabled. Zero Coefficients--Read/write control bit that continuously zeros all coefficients when set; allows normal coefficient updates, if enabled, when cleared. This behavior differs slightly from the similar function (zero_coefficients) of the FFE and EP filters. adapt_coefficents zero_coefficients 48 N8960DSB BT8960 Single-Chip 2B1Q Transceiver zero_output 3.0 Registers 3.1 Conventions Zero Output--Read/write control bit which, when set, zeros the echo replica before subtraction from the input signal. Achieves the affect of disabling or bypassing the echo cancellation function. Does not disable coefficient adaptation. When cleared, normal echo Canceller operation is performed. Adaptation Gain--Read/write binary field which specifies the adaptation gain. adapt_gain[1,0] 00 01 10 11 adapt_gain[1,0] Normalized Gain 1 4 64 512 3.2.10 0x09--Nonlinear Echo Canceller Modes Register (nonlinear_ec_modes) 7 negate_symbol 6 5 4 3 adapt_ coefficients 2 zero_coefficients 1 zero_output 0 adapt_gain symbol_delay[2] symbol_delay[1] symbol_delay[0] negate_symbol Negate Symbol--Read/write control bit which, when set, inverts (2's complement) the receive signal path at the output of the nonlinear echo canceller. When cleared, the signal path is unaffected. This function is independent of all other NEC mode settings. Symbol Delay--Read/write binary field which specifies the number of symbol delays inserted in the transmit symbol input path. Adapt Coefficients--Same function as LEC Modes Register [linear_ec_modes; 0x08]. Zero Coefficients--Same function as LEC Modes Register. Zero Output--Same function as LEC Modes Register. Adaptation Gain--Read/write control bit which specifies the adaptation gain. When set, the adaptation gain is eight times higher than when cleared. symbol_delay[2:0] adapt_coefficients zero_coefficients zero_output adapt_gain N8960DSB 49 3.0 Registers 3.1 Conventions BT8960 Single-Chip 2B1Q Transceiver 3.2.11 0x0A--Decision Feedback Equalizer Modes Register (dfe_modes) 7 - 6 - 5 - 4 - 3 adapt_ coefficients 2 zero_coefficients 1 zero_output 0 adapt_gain adapt_coefficents Adapt Coefficients--Read/write control bit which enables coefficient adaptation when set; disables/freezes adaptation when cleared. Coefficient values are preserved when adaptation is disabled. Zero Coefficients--Read/write control bit which continuously zeros all coefficients when set; allows normal coefficient updates, if enabled, when cleared. Zero Output--Read/write control bit which, when set, zeros the equalizer correction signal before subtraction from the input signal. Achieves the affect of disabling or bypassing the equalization function. Does not disable coefficient adaptation. When cleared, normal equalizer operation is performed. Adaptation Gain--Read/write control bit which specifies the adaptation gain. When set, the adaptation gain is eight times higher than when cleared. zero_coefficients zero_output adapt_gain 3.2.12 0x0B--Transmitter Modes Register (transmitter_modes) 7 - 6 5 4 transmitter_off 3 htur_lfsr 2 data_source[2] 1 data_source[1] 0 data_source[0] isolated_pulse[1] isolated_pulse[0] isolated_pulse[1,0] Isolated Pulse Level Select--Read/write binary field that selects one of four output pulse levels while in the isolated pulse transmitter mode. isolated_pulse[1,0] 00 01 10 11 Output Pulse Level -3 -1 +3 +1 transmitter_off Transmitter Off--Read/write control bit that zeros the output of the transmitter when set; allows normal transmitter operation (as defined by data_source[2:0]) when cleared. Remote Unit (HTU-R/NTU) Polynomial Select--Read/write control bit selects one of two feedback polynomials for the transmit scrambler. When set, this bit selects the remote unit transmit polynomial (x-23 + x-18 + 1); when cleared, it selects the local unit (HTU-C/LTU) polynomial (x-23 + x-5 + 1). Data Source--Read/write binary field that selects the data source and mode of the transmitter output. The transmitter must be enabled (transmitter_off = 0) for these modes to be active. htur_lfsr data_source[2:0] 50 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 3.0 Registers 3.1 Conventions data_source [2:0] 000 Transmitter Mode Isolated pulse. Level selected by isolated_pulse[1:0]. The meter timer must be enabled and in the continuous mode. The pulse repetition interval is determined by the meter timer countdown interval. Four-level scrambled detector loopback. Sign and magnitude bits from the receiver detector are scrambled and looped back to the transmitter. Feedback polynomial determined by the htur_lfsr control bit. Four-level unscrambled data. Transmits the four-level (2B1Q) sign and magnitude bits from the channel unit transmit interface without scrambling. Four-level scrambled ones. Transmits a scrambled, constant high logic level as a fourlevel (2B1Q) signal. Feedback polynomial determined by the htur_lfsr control bit. Reserved. Four-level scrambled data. Scrambles and transmits the four-level (2B1Q) sign and magnitude bits from the channel unit transmit interface. Feedback polynomial determined by the htur_lfsr control bit. Two-level unscrambled data. Constantly forces the magnitude bit from the channel unit transmit interface to a logic zero and transmits the resulting two-level signal (as determined by the sign bit) without scrambling. Valid output levels limited to +3, -3. Two-level scrambled ones. Transmits a scrambled, constant high-logic level as a twolevel signal. Feedback polynomial determined by the htur_lfsr control bit. Scrambler is run at the symbol rate (half-bit rate) to produce the sign bit of the transmitted signal while the magnitude bit is sourced with a constant logic zero. Valid output levels limited to +3, -3. 001 010 011 100 101 110 111 N8960DSB 51 3.0 Registers 3.1 Conventions BT8960 Single-Chip 2B1Q Transceiver 3.2.13 0x0C--Timer Restart Register (timer_restart) Independent read/write restart bits, one for each of the eight internal timers. Setting an individual bit causes the associated timer to be reloaded with the contents of its interval register. For the four symbol-rate timers (meter, snr, t3, t4), reloading will occur within one symbol period. For the four startup timers (sut1-4), reloading will occur within 1,024 symbol periods. Once reloaded, the restart bit is automatically cleared. If a restart bit is set and then cleared (by writing a logic zero) before the reload actually takes place, no timer reload will occur. Once reloaded, if enabled in the Timer Enable Register [timer_enable; 0x0D], the timer will begin counting down toward zero; otherwise, it will hold at the interval register value. 7 t4 6 t3 5 snr 4 meter 3 sut4 2 sut3 1 sut2 0 sut1 t4 t3 snr meter sut4 sut3 sut2 sut1 General Purpose Timer 4 General Purpose Timer 3 SNR Alarm Timer Meter Timer Startup Timer 4 Startup Timer 3 Startup Timer 2 Startup Timer 1 3.2.14 0x0D--Timer Enable Register (timer_enable) Independent read/write enable bits, one for each of the eight internal timers. When any individual bit is set, the corresponding timer is enabled for counting down from its current value toward zero. For the four symbol-rate timers (meter, snr, t3, t4), counting will begin within one symbol period. For the four startup timers (sut1-4), counting will begin within 1,024 symbol periods. When an enable bit is cleared, the timer is disabled from counting while it holds its current value. If an enable bit is set and then cleared before a count actually takes place, no timer countdown will occur. 7 t4 6 t3 5 snr 4 meter 3 sut4 2 sut3 1 sut2 0 sut1 t4 t3 snr meter sut4 sut3 sut2 sut1 General Purpose Timer 4 General Purpose Timer 3 SNR Alarm Timer Meter Timer Startup Timer 4 Startup Timer 3 Startup Timer 2 Startup Timer 1 52 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 3.0 Registers 3.1 Conventions 3.2.15 0x0E--Timer Continuous Mode Register (timer_continuous) Independent read/write mode bits, one for each of the eight internal timers. When any individual bit is set, the corresponding timer is placed in the continuous count mode. While in this mode, after reaching the zero count, an enabled timer will reload the contents of its interval register and continue counting. When a mode bit is cleared, the timer is taken out of the continuous mode. While in this configuration, after reaching the zero count, an enabled timer will simply stop counting and remain at zero. 7 t4 6 t3 5 snr 4 meter 3 sut4 2 sut3 1 sut2 0 sut1 3.2.16 0x0F--Test Register (reserved2) A 1-byte read/write register used for device testing by Rockwell. This register is automatically initialized to 0x00 upon RST assertion and initial power application. This register must be initialized according to the device driver provided by Rockwell. 3.2.17 0x10, 0x11--Startup Timer 1 Interval Register (sut1_low, sut1_high) A 2-byte read/write register stores the countdown interval for Startup Timer 1 in unsigned binary format. Each increment represents 1,024 symbol periods. The contents of this register are automatically loaded into its associated timer after the timer's timer_restart bit is set, or after it counts down to zero while in the continuous mode. 3.2.18 0x12, 0x13--Startup Timer 2 Interval Register (sut2_low, sut2_high) A 2-byte read/write register stores the countdown interval for Startup Timer 2 in unsigned binary format. Each increment represents 1,024 symbol periods. The contents of this register are automatically loaded into its associated timer after the timer's timer_restart bit is set, or after it counts down to zero while in the continuous mode. 3.2.19 0x14, 0x15--Startup Timer 3 Interval Register (sut3_low, sut3_high) A 2-byte read/write register stores the countdown interval for Startup Timer 3 in unsigned binary format. Each increment represents 1,024 symbol periods. The contents of this register are automatically loaded into its associated timer after the timer's timer_restart bit is set, or after it counts down to zero while in the continuous mode. 3.2.20 0x16, 0x17--Startup Timer 4 Interval Register (sut4_low, sut4_high) A 2-byte read/write register stores the countdown interval for Startup Timer 4 in unsigned binary format. Each increment represents 1,024 symbol periods. The contents of this register are automatically loaded into its associated timer after the timer's timer_restart bit is set, or after it counts down to zero while in the continuous mode. 3.2.21 0x18, 0x19--Meter Timer Interval Register (meter_low, meter_high) A 2-byte read/write register stores the countdown interval for the Meter Timer in unsigned binary format. Each increment represents one symbol period. The contents of this register are automatically loaded into its associated timer after the timer's timer_restart bit is set, or after it counts down to zero while in the continuous mode. N8960DSB 53 3.0 Registers 3.1 Conventions BT8960 Single-Chip 2B1Q Transceiver 3.2.22 0x20--Test Register (reserved9) A 1-byte read/write register used for device testing by Rockwell. This register is automatically initialized to 0x00 upon RST assertion and initial power application. This register must be initialized according to the device driver provided by Rockwell. 3.2.23 0x1A, 0x1B--SNR Alarm Timer Interval Register (snr_timer_low, snr_timer_high) A 2-byte read/write register stores the countdown interval for the SNR Alarm Timer in unsigned binary format. Each increment represents one symbol period. The contents of this register are automatically loaded into its associated timer after the timer's timer_restart bit is set, or after it counts down to zero while in the continuous mode. 3.2.24 0x1C, 0x1D--General Purpose Timer 3 Interval Register (t3_low, t3_high) A 2-byte read/write register stores the countdown interval for General Purpose Timer 3 in unsigned binary format. Each increment represents one symbol period. The contents of this register are automatically loaded into its associated timer after the timer's timer_restart bit is set, or after it counts down to zero while in the continuous mode. 3.2.25 0x1E, 0x1F--General Purpose Timer 4 Interval Register (t4_low, t4_high) A 2-byte read/write register stores the countdown interval for General Purpose Timer 4 in unsigned binary format. Each increment represents one symbol period. The contents of this register are automatically loaded into its associated timer after the timer's timer_restart bit is set, or after it counts down to zero while in the continuous mode. 54 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 3.0 Registers 3.1 Conventions 3.2.26 0x21--ADC Control Register (adc_control) 7 - 6 - 5 loop_back[1] 4 loop_back[0] 3 - 2 gain[2] 1 gain[1] 0 gain[0] loop_back[1,0] Loopback Control--Read/write binary field specifying if loopback is enabled, and the type of loopback that is enabled. During transmitting loopback, the differential receiver inputs (RXP, RXN) are disabled. The loopback path is intended to go from the transmitter outputs (TXP, TXN), through the external hybrid circuit, back into the differential receiver balance inputs (RXBP, RXBN). During silent loop back, the transmitter is turned off, and the output of the pulse-shaping filter in the transmit section is internally connected to the input of the ADC in the receive section. loop_back[1,0] 00 01 10 11 Function Normal Operation (Loop Back Disabled) Hybrid Inputs Disabled (RXBP, RXBN) Transmitting Loopback Silent Loop Back gain[2:0] Gain Control--Read/write binary field specifies the gain of the VGA. gain[2:0] 000 001 010 011 100 101 110 111 VGA Gain 0dB 3 dB 6 dB 9 dB 12 dB 15 dB 15 dB 15 dB N8960DSB 55 3.0 Registers 3.1 Conventions BT8960 Single-Chip 2B1Q Transceiver 3.2.27 0x22--PLL Modes Register (pll_modes) 7 clk_freq[1] 6 clk_freq[0] 5 negate_symbol 4 3 2 freeze_pll 1 pll_gain[1] 0 pll_gain[0] phase_detector_ phase_detector_ gain[1] gain[0] clk_freq[1,0] Clock Frequency Select--Read/write binary field specifies one of four data rate ranges for BT8960 operation. The 00 state is automatically selected by RST assertion and upon initial power application. The crystal or external clock frequency must be equal to 32 times the data rate. clk_freq[1,0] 00 01 10 11 Range Data Rate 221 to 252kbps Above 352 kbps 160 to 221 kbps Reserved phase_detector_ gain[1,0] Phase Detector Gain--Read/write binary field specifies one of four gain settings for the timing-recovery phase detector function. phase_detector_gain[1,0] 00 01 10 11 Normalized Gain 1 2 4 Reserved freeze_pll Freeze PLL--Read/write control bit. When set, this bit zeros the proportional term of the loop compensation filter and disables accumulator updates causing the PLL to hold its current frequency. When cleared, proportional term effects and accumulator updates are enabled allowing the PLL to track the phase of the incoming data. PLL Gain--Read/write binary field specifies the gain (proportional and integral coefficients) of the loop compensation filter. Normalized Proportional Coefficients 1 4 16 64 pll_gain[1,0] pll_gain[1:0] 00 01 10 11 Normalized Integral Coefficients 1 32 256 4096 56 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 3.0 Registers 3.1 Conventions 3.2.28 0x23--Test Register (reserved10) A 3-byte read/write register used for device testing by Rockwell. This register is automatically initialized to 0x000000 upon RST assertion and initial power application. This register must be initialized according to the device driver provided by Rockwell. 3.2.29 0x24, 0x25--Timing Recovery PLL Phase Offset Register (pll_phase_offset_low, pll_phase_offset_high) A 2-byte read/write register interpreted as a 16-bit, 2's-complement number. The value of this register is subtracted from the output of the timing-recovery phase detector after the phase-detector meter but before the loop compensation filter. 3.2.30 0x26, 0x27--Receiver DC Offset Register (dc_offset_low, dc_offset_high) A 2-byte read/write register interpreted as a 16-bit, 2's-complement number. The value of this register is subtracted from the receiver signal path at the output of the digital front end's format conversion block, ahead of the DC level and signal level meters. 3.2.31 0x28--Transmitter Calibration Register (tx_calibrate) 7 - 6 - 5 tx_calibrate[3] 4 tx_calibrate[2] 3 tx_calibrate[1] 2 tx_calibrate[0] 1 - 0 - tx_calibrate[3:0] Transmit Calibrate--4-bit, 2's-complement, read-only field containing the nominal setting for the transmitter gain. The value of the Transmit Calibration Register is set during manufacturing testing by Rockwell and corresponds to the value required to operate the BT8960 at a nominal 13.5 dBm transmit power, assuming the recommended transformer coupling/hybrid circuit is used. Users may override this calibration by writing their own value into the Transmitter Gain Register [tx_gain; 0x29]. N8960DSB 57 3.0 Registers 3.1 Conventions BT8960 Single-Chip 2B1Q Transceiver 3.2.32 0x29--Transmitter Gain Register (tx_gain) 7 - 6 - 5 tx_gain[3] 4 tx_gain[2] 3 tx_gain[1] 2 tx_gain[0] 1 - 0 - tx_gain[3:0] Transmit Gain--A 4-bit, 2's-complement, read/write field controlling the transmitter gain. Upon initialization, the value in the Transmitter Calibration Register [tx_calibrate; 0x28] may be written into this register by software to set the transmitter gain to the nominal value, or the user may set it to another desired value. tx_gain[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 Relative Transmitter Gain (dB) -1.60 -1.36 -1.13 -0.91 -0.69 -0.48 -0.27 -0.07 0.13 0.32 0.51 0.70 0.88 1.05 1.23 1.40 58 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 3.0 Registers 3.1 Conventions 3.2.33 0x2A, 0x2B--Noise-Level Histogram Threshold Register (noise_histogram_th_low, noise_histogram_th_high) Two-byte read/write register interpreted as a 16-bit, 2's-complement number. The range of meaningful values is limited to positive integers between 0x0000 and 0x7FFF. The value of this register is compared to the absolute value of the slicer error signal produced by the detector. A count of error samples that exceed this threshold (greater than) is accumulated in the noise-level histogram meter. 3.2.34 0x2C, 0x2D--Error Predictor Pause Threshold Register (ep_pause_th_low, ep_pause_th_high) Two-byte read/write register interpreted as a 16-bit, 2's-complement number. The range of meaningful values is limited to positive integers between 0x0000 and 0x7FFF. The value of this register is compared to the absolute value of the slicer error signal produced by the detector. The result of this comparison (slicer error greater than this threshold) is used to initiate a pause condition by zeroing the output of the error predictor correction signal before subtraction from the receive signal path. Error predictor coefficient updates are not affected. The pause condition lasts for a fixed 5-symbol period from the time the threshold was last exceeded. 3.2.35 0x2E--Scrambler Synchronization Threshold Register (scr_sync_th) A 7-bit read/write register representing an unsigned binary number. The contents of this register are used to test for scrambler synchronization during the automatic-scrambler synchronization mode of the symbol detector. The test passes when the count of equivalent scrambler and detector output bits exceeds (greater than) the value of this register. When the auto-scrambler sync mode is not enabled, the contents of this register are not used. 7 - 6 D[6] 5 D[5] 4 D[4] 3 D[3] 2 D[2] 1 D[1] 0 D[0] 3.2.36 0x30, 0x31--Far-End High Alarm Threshold Register (far_end_high_alarm_th_low, far_end_high_alarm_th_high) A 2-byte read/write register interpreted as a 16-bit, 2's-complement number. The range of meaningful values is limited to positive integers between 0x0000 and 0x7FFF. The value of this register is compared to the value of the far-end level meter. If the meter reading exceeds (greater than) this threshold, the high_felm interrupt flag is set in the IRQ Source Register [irq_source; 0x05]. 3.2.37 0x32, 0x33--Far-End Low Alarm Threshold Register (far_end_low_alarm_th_low, far_end_low_alarm_th_high) A 2-byte read/write register interpreted as a 16-bit, 2's-complement number. The range of meaningful values is limited to positive integers between 0x0000 and 0x7FFF. The value of this register is compared to the value of the far-end level meter. If the meter reading exceeds (less than) this threshold, the low_felm interrupt flag is set in the IRQ Source Register [irq_source; 0x05]. N8960DSB 59 3.0 Registers 3.1 Conventions BT8960 Single-Chip 2B1Q Transceiver 3.2.38 0x34, 0x35--SNR Alarm Threshold Register (snr_alarm_th_low, snr_alarm_th_high) A 2-byte read/write register interpreted as a 16-bit, 2's-complement number. The range of meaningful values is limited to positive integers between 0x0000 and 0x7FFF. The value of this register is compared to the value of the SNR alarm meter. If the meter reading exceeds (greater than) this threshold, the low_snr interrupt flag is set in the IRQ Source Register [irq_source; 0x05]. 3.2.39 0x36, 0x37--Cursor Level Register (cursor_level_low, cursor_level_high) A 2-byte read/write register interpreted as a 16-bit, 2's-complement number. The range of meaningful values is limited to positive integers between 0x0000 and 0x2AAA (one-third of the maximum positive value). The value of this register represents the expected level of a noise-free +1 receive symbol at the output of the DFE. It is multiplied by 2 to produce the positive and negative slicing levels, in addition to zero, used by the symbol detector in four-level slicing mode. This value is also used to scale the detector output when computing the equalizer error and slicer error signals. The detected symbol (-3, -1, +1, +3) is multiplied by the value of this register to produce the scaled output. 3.2.40 0x38, 0x39--DAGC Target Register (dagc_target_low, dagc_target_high) A 2-byte read/write register interpreted as a 16-bit, 2's-complement number. The range of meaningful values is limited to positive integers between 0x0000 and 0x7FFF. The value of this register is subtracted from the absolute value of the receive signal at the output of the DAGC function. The difference is used as the error input to the DAGC while in the self-adaptation mode. In the DAGC's equalizer-error adaptation mode, the contents of this register are not used. 60 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 3.0 Registers 3.1 Conventions 3.2.41 0x3A--Symbol Detector Modes Register (detector_modes) 7 6 5 4 3 two_level 2 lfsr_lock 1 htur_lfsr 0 descr_on enable_peak_det output_mux_con output_mux_con scr_out_to_dfe ector trol[1] trol[0] enable_peak_ detector Enable Peak Detector--Read/write control bit that enables the peak detection function when set; disables the function when cleared. When enabled, the peak detector output overrides the slicer output if the peak detection criteria are met. If the criteria are not met, or if the function is disabled, the slicer output is used and peak detector output is ignored. Output Multiplexer Control--Read/write binary field that selects the source of the detector output connected to the channel unit receive interface. output_mux_control[1,0] 00 01 10 11 output_mux_ control[1,0] Detector Output to CU Receive Interface Same as scr_out_to_dfe selection. Transmitter loopback output from CU transmit interface. Scrambler/descrambler output. Reserved. scr_out_to_dfe Scrambler Output to DFE--Read/write control bit that selects the source of the detector output connected to the DFE and timing recovery module inputs, and the transmitter's detector loopback input. When set, this bit selects the scrambler/descrambler function; when cleared, it selects the slicer/peak detector output. Two-Level Mode--Read/write control bit that selects two-level mode when set, four-level mode when cleared. Affects the slicer and the scrambler/descrambler function. In two-level mode, the slicer uses a single threshold set at zero to recover sign bits only; all magnitude information is lost. Scrambler/descrambler updates are slowed to the symbol rate (half the normal bit rate) to process only sign information as well; all magnitude output bits are sourced with a constant logic zero value producing two-level symbols constrained to +3 and -3 values. In 4-level mode, the slicer uses two thresholds derived from the Cursor Level Register [cursor_level_low, cursor_level_high; 0x36-0x37], as well as the zero threshold, to recover both sign and magnitude information. The scrambler/descrambler is updated at the full bit rate to process both sign and magnitude bits as well. LFSR Lock--Read/write control bit that enables the auto scrambler synchronization mode (lfsr_lock) in the detector when set; disables this mode when cleared. Affects the behavior of the scrambler/descrambler function, overriding the descr_on setting. When enabled, the scrambler/descrambler is forced into the descrambler mode for 23 cycles. It is then switched to the scrambled-ones mode for 128 cycles. While in this mode, the outputs of the scrambler and the slicer/peak detector are compared against one another. The number of equivalent bits (equal comparisons) is accumulated and compared to the value of the scrambler synchronization threshold register [scr_sync_th; 0x2E]. At any time during the 128 cycles, if the count exceeds the threshold (greater than), the sync interrupt flag is set in the IRQ Source Register [irq_source; 0x05] and the process terminates with the scrambler/descrambler left in the scrambled-ones mode. (The sync interrupt flag canN8960DSB two_level lfsr_lock 61 3.0 Registers 3.1 Conventions BT8960 Single-Chip 2B1Q Transceiver not be cleared while lfsr_lock remains high.) After 128 cycles, if the threshold is not exceeded, the accumulator is cleared, the scrambler/descrambler re-enters the descrambler mode for another 23 cycles, and the process repeats until either sync is achieved or this mode is disabled. Once disabled, the sync interrupt flag can be cleared (if active) and the scrambler/descrambler returns to the mode specified by descr_on. htur_lfsr Remote Unit (HTU-R/NTU) Polynomial Select--Read/write control bit that selects one of two feedback polynomials for the scrambler/descrambler. When set, this bit selects the remote unit (HTU-R/NTU) receive polynomial (x-23 + x-5 + 1); when cleared, is selects the local unit (HTU-C/LTU) polynomial (x-23 + x-18 + 1). Descrambler/Scrambler Select--Read/write control bit that configures the scrambler/descrambler function as a descrambler when set, and as a scrambler when cleared. As a scrambler, this bit can only generate a scrambled all ones sequence (constant high logic-level input); all incoming data is ignored. In the auto scrambler synchronization mode (lfsr_lock = 1), this selection is overwritten though the value of the control bit is unaffected. descr_on 3.2.42 0x3B--Peak Detector Delay Register (peak_detector_delay) A 4-bit read/write register interpreted as an unsigned binary number. Specifies a number of additional symbol delays inserted in the peak detector input path of the symbol detector. Must be set to a value that equalizes the total path delay in each of the peak detector and slicer input paths according to the following formula: peak detector delay register value = DAGC delays + FFE delays - fixed peak detector input delays. The DAGC and FFE delays are not fixed, but result from the microprogrammed implementation of these functions. If used unmodified, they equal 0 and 7, respectively. The fixed peak detector input delay is equal to 3. 7 - 6 - 5 - 4 - 3 D[3] 2 D[2] 1 D[1] 0 D[0] 3.2.43 0x3C--Digital AGC Modes Register (dagc_modes) 7 - 6 - 5 - 4 - 3 - 2 eq_error_ adaptation 1 adapt_coefficient 0 adapt_gain eq_error_ adaptation Equalizer Error Adaptation--Read/write control bit that selects between the equalizer error adaptation mode when set, and the self-adaptation mode when cleared. Equalizer error adaptation uses the equalizer error signal produced by the slicer as the DAGC error input signal. In self adaptation, the value of the DAGC Target Register [dagc_target_low, dagc_target_high; 0x38-0x39] is subtracted from the absolute value of the receive signal at the output of the DAGC, and this difference is used as the error input signal. Adapt Coefficients--Read/write control bit that enables coefficient adaptation when set; disables/freezes adaptation when cleared. Coefficient values are preserved when adaptation is disabled. Adaptation Gain--Read/write control bit that specifies the adaptation gain. When set, the adaptation gain is eight times higher than when cleared. adapt_coefficient adapt_gain 62 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 3.0 Registers 3.1 Conventions 3.2.44 0x3D--Feed Forward Equalizer Modes Register (ffe_modes) 7 - 6 - 5 - 4 - 3 2 1 adapt_ coefficents 0 adapt_gain adapt_last_coeff zero_coefficents adapt_last_coeff Adapt Last Coefficient--Read/write control bit enables adaptation of the last (oldest) coefficient only when set; allows all coefficient adaptation when cleared. Overall coefficient adaptation must be enabled (adapt_coefficients = 1) for this behavior to occur. If coefficient adaptation is disabled (adapt_coefficients = 0), the value of this control bit is not used. Zero Coefficients--Read/write control bit which, with coefficient adaptation enabled (adapt_coefficients = 1), continuously zeros all coefficients when set; allows normal coefficient updates when cleared. If coefficient adaptation is disabled (adapt_coefficients = 0), this control bit has no affect. This behavior differs slightly from the similar function (zero_coefficients) of the LEC, NEC, and DFE filters. Adapt Coefficients--Read/write control bit enables coefficient adaptation when set; disables/freezes adaptation when cleared. Coefficient values are preserved when adaptation is disabled. This overall coefficient adaptation must be enabled for adapt_last_coeff to have an affect. Adaptation Gain--Read/write control bit specifies the adaptation gain. When set, the adaptation gain is four times higher than when cleared. zero_coefficients adapt_coefficents adapt_gain 3.2.45 0x3E--Error Predictor Modes Register (ep_modes) 7 - 6 - 5 - 4 - 3 zero_output 2 zero_coefficients 1 adapt_ coefficients 0 adapt_gain zero_output Zero Output--Read/write control bit which, when set, zeros the error predictor correction signal before subtraction from the input signal. Achieves the affect of disabling, or bypassing, the error predictor function. Does not disable coefficient adaptation. When cleared, normal error predictor operation is performed. Zero Coefficients--Read/write control bit which, with coefficient adaptation enabled (adapt_coefficients = 1), continuously zeros all coefficients when set; allows normal coefficient updates when cleared. If coefficient adaptation is disabled (adapt_coefficients = 0), this control bit has no affect. This behavior differs slightly from the similar function (zero_coefficients) of the LEC, NEC, and DFE filters. Adapt Coefficients--Read/write control bit enables coefficient adaptation when set; disables/freezes adaptation when cleared. Coefficient values are preserved when adaptation is disabled. Adaptation Gain--Read/write control bit specifies the adaptation gain. When set, the adaptation gain is four times higher than when cleared. zero_coefficients adapt_coefficents adapt_gain N8960DSB 63 3.0 Registers 3.1 Conventions BT8960 Single-Chip 2B1Q Transceiver 3.2.46 0x40, 0x41--Phase Detector Meter Register (pdm_low, pdm_high) A 2-byte read-only register containing the 16 MSBs of the 26-bit, 2's-complement phase detector meter accumulator. This meter sums the output of the timing recovery module's phase detector--prior to being offset by the Phase Offset Register [pll_phase_offset_low, pll_phase_offset_high; 0x24, 0x25]--over each Meter Timer countdown interval. Automatically loaded at the end of each interval, the meter register must be read low byte first, followed by high byte, unseparated by any other meter-register read access. 7 D[17] D[25] 6 D[16] D[24] 5 D[15] D[23] 4 D[14] D[22] 3 D[13] D[21] 2 D[12] D[20] 1 D[11] D[19] 0 D[10] D[18] 3.2.47 0x42--Overflow Meter Register (overflow_meter) A single-byte read-only register containing all 8 bits of the unsigned overflow meter accumulator. This meter counts the number of ADC overflow conditions which occur during each Meter Timer countdown interval, limited to a maximum count of 255 (0xFF). The meter register is automatically loaded at the end of each countdown interval. 7 D[7] 6 D[6] 5 D[5] 4 D[4] 3 D[3] 2 D[2] 1 D[1] 0 D[0] 3.2.48 0x44, 0x45--DC Level Meter Register (dc_meter_low, dc_meter_high) A 2-byte read-only register containing the 16 MSBs of the 32-bit, 2's-complement DC-level meter accumulator. This meter sums the value of the receive signal input path--after format conversion and DC offset correction but before echo cancellation--over each Meter Timer countdown interval. Automatically loaded at the end of each interval, the meter register must be read low byte first, followed by high byte, unseparated by any other meter-register read access. 7 D[23] D[31] 6 D[22] D[30] 5 D[21] D[29] 4 D[20] D[28] 3 D[19] D[27] 2 D[18] D[26] 1 D[17] D[25] 0 D[16] D[24] 64 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 3.0 Registers 3.1 Conventions 3.2.49 0x46, 0x47--Signal Level Meter Register (slm_low, slm_high) A 2-byte read-only register containing 16 MSBs of the 32-bit unsigned signal-level meter accumulator. This meter sums the absolute value of the receive signal input path--after format conversion and DC offset correction but before echo cancellation (same point as the DC level meter)--over each Meter Timer countdown interval. Automatically loaded at the end of each interval, the meter register must be read low byte first, followed by high byte, unseparated by any other meter-register read access. 7 D[23] D[31] 6 D[22] D[30] 5 D[21] D[29] 4 D[20] D[28] 3 D[19] D[27] 2 D[18] D[26] 1 D[17] D[25] 0 D[16] D[24] 3.2.50 0x48, 0x49--Far-End Level Meter Register (felm_low, felm_high) A 2-byte read-only register containing 16 MSBs of the 32-bit unsigned far-end level meter accumulator. This meter sums the absolute value of the receive signal path--after echo cancellation but before the DAGC function--over each Meter Timer countdown interval. Automatically loaded at the end of each interval, the meter register must be read low byte first, followed by high byte, unseparated by any other meter-register read access. 7 D[23] D[31] 6 D[22] D[30] 5 D[21] D[29] 4 D[20] D[28] 3 D[19] D[27] 2 D[18] D[26] 1 D[17] D[25] 0 D[16] D[24] 3.2.51 0x4A, 0x4B--Noise Level Histogram Meter Register (noise_histogram_low, noise_histogram_high) A 2-byte read-only register containing all 16 bits of the unsigned noise-level histogram meter accumulator. This meter counts the number of high-noise-level conditions which occur during each Meter Timer countdown interval. A high-noise-level condition is defined as the absolute value of the slicer error signal exceeding (greater than) the threshold specified in the Noise-level Histogram Threshold Register [0x2A, 2B]. Automatically loaded at the end of each countdown interval, the meter register must be read low byte first, followed by high byte, unseparated by any other meter-register read access. 7 D[7] D[15] 6 D[6] D[14] 5 D[5] D[13] 4 D[4] D[12] 3 D[3] D[11] 2 D[2] D[10] 1 D[1] D[9] 0 D[0] D[8] N8960DSB 65 3.0 Registers 3.1 Conventions BT8960 Single-Chip 2B1Q Transceiver 3.2.52 0x4C, 0x4D--Bit Error Rate Meter Register (ber_meter_low, ber_meter_high) A 2-byte read-only register containing all 16 bits of the unsigned bit-error-rate meter accumulator. This meter counts the number of error-free bits recovered by the detector during each Meter Timer countdown interval. An error-free bit is defined as a match (equal comparison) of the detector's slicer/peak detector output and its scrambler/descrambler output, when operating as a scrambler. When operating as a descrambler, the meter simply counts the number of logic ones produced by the descrambler. The meter register is automatically loaded at the end of each countdown interval, and must be read low byte first, followed by high byte, unseparated by any other meter-register read access. 7 D[7] D[15] 6 D[6] D[14] 5 D[5] D[13] 4 D[4] D[12] 3 D[3] D[11] 2 D[2] D[10] 1 D[1] D[9] 0 D[0] D[8] 3.2.53 0x4E--Symbol Histogram Meter Register (symbol_histogram) A single-byte read-only register containing 8 MSBs of the 16-bit unsigned symbol histogram meter accumulator. This meter counts the number of plus-one or minus-one symbols (+1, -1) detected during each Meter Timer countdown interval. No increment occurs when a plus-three or minus-three symbol (+3, -3) is detected. The meter register is automatically loaded at the end of each countdown interval. 7 D[7] 6 D[6] 5 D[5] 4 D[4] 3 D[3] 2 D[2] 1 D[1] 0 D[0] 3.2.54 0x50, 0x51--Noise Level Meter Register (nlm_low, nlm_high) A 2-byte read-only register containing 16 MSBs of the 32-bit unsigned noise-level meter accumulator. This meter sums the absolute value of the detector's slicer-error signal over each Meter Timer countdown interval. Automatically loaded at the end of each interval, the meter register must be read the low byte first, followed by high byte, unseparated by any other meter-register read access. 7 D[23] D[31] 6 D[22] D[30] 5 D[21] D[29] 4 D[20] D[28] 3 D[19] D[27] 2 D[18] D[26] 1 D[17] D[25] 0 D[16] D[24] 66 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 3.0 Registers 3.1 Conventions 3.2.55 0x5E, 0x5F-- PLL Frequency Register (pll_frequency_low, pll_frequency_high) A 2-byte read/write register comprising the 16 MSBs of the 31-bit, 2's-complement timing recovery loop compensation filter accumulator. Treated much like a meter register, the frequency register must be read low byte first, followed by high byte, unseparated by any timing-function or meter-register read access. Writes must occur in the same order, with the low byte written first, followed by the high byte. Write accesses may be separated by any number of other read or write accesses. 7 D[22] D[30] 6 D[21] D[29] 5 D[20] D[28] 4 D[19] D[27] 3 D[18] D[26] 2 D[17] D[25] 1 D[16] D[24] 0 D[15] D[23] 3.2.56 0x70--LEC Read Tap Select Register (linear_ec_tap_select_read) A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 59 decimals. When written, it causes the selected 32-bit coefficient of the LEC to be subsequently loaded into the Access Data Register [access_data_byte[3:0]; 0x7C-0x7F] within two symbol periods. Does not affect the value of the coefficient. 7 - 6 - 5 D[5] 4 D[4] 3 D[3] 2 D[2] 1 D[1] 0 D[0] 3.2.57 0x71--LEC Write Tap Select Register (linear_ec_tap_select_write) A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 59 decimals. When written, it causes all 32 bits of the Access Data Register [access_data_byte[3:0]; 0x7C-0x7F] to be subsequently written to the selected LEC coefficient within two symbol periods. Does not affect the value of the access data register. 7 - 6 - 5 D[5] 4 D[4] 3 D[3] 2 D[2] 1 D[1] 0 D[0] 3.2.58 0x72--NEC Read Tap Select Register (nonlinear_ec_tap_select_read) A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimals. When written, it causes the selected 14-bit coefficient of the NEC to be subsequently loaded into the lowestorder bits of the Access Data Register [access_data_byte[3:0]; 0x7C-0x7F] within two symbol periods. Does not affect the value of the coefficient. 7 - 6 - 5 D[5] 4 D[4] 3 D[3] 2 D[2] 1 D[1] 0 D[0] N8960DSB 67 3.0 Registers 3.1 Conventions BT8960 Single-Chip 2B1Q Transceiver 3.2.59 0x73--NEC Write Tap Select Register (nonlinear_ec_tap_select_write) A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimals. When written, it causes the lowest-order 14 bits of the Access Data Register [access_data_byte[3:0]; 0x7C- 0x7F] to be subsequently written to the selected NEC coefficient within two symbol periods. Does not affect the value of the access data register. 7 - 6 - 5 D[5] 4 D[4] 3 D[3] 2 D[2] 1 D[1] 0 D[0] 3.2.60 0x74--DFE Read Tap Select Register (dfe_tap_select_read) A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 57 decimals. When written, it causes the selected 16-bit coefficient of the DFE to be subsequently loaded into the lowestorder bits of the Access Data Register [access_data_byte[3:0]; 0x7C-0x7F] within two symbol periods. Does not affect the value of the coefficient. 7 - 6 - 5 D[5] 4 D[4] 3 D[3] 2 D[2] 1 D[1] 0 D[0] 3.2.61 0x75--DFE Write Tap Select Register (dfe_tap_select_write) A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 57 decimals. When written, it causes the lowest-order 16 bits of the Access Data Register [access_data_byte[3:0]; 0x7C- 0x7F] to be subsequently written to the selected DFE coefficient within two symbol periods. Does not affect the value of the access data register. 7 - 6 - 5 D[5] 4 D[4] 3 D[3] 2 D[2] 1 D[1] 0 D[0] 3.2.62 0x76--Scratch Pad Read Tap Select (sp_tap_select_read) A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimals. When written, it causes the selected 8-bit scratch pad memory location to be subsequently loaded into the lowest-order bits of the Access Data Register [access_data_byte[3:0]; 0x7C-0x7F] within two symbol periods. Does not affect the value of the memory. 7 - 6 - 5 D[5] 4 D[4] 3 D[3] 2 D[2] 1 D[1] 0 D[0] 68 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 3.0 Registers 3.1 Conventions 3.2.63 0x77--Scratch Pad Write Tap Select (sp_tap_select_write) A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimals. When written, it causes the lowest-order 8 bits of the Access Data Register [access_data_byte[3:0]; 0x7C- 0x7F] to be subsequently written to the selected scratch pad memory location within two symbol periods. Does not affect the value of the access data register. 7 - 6 - 5 D[5] 4 D[4] 3 D[3] 2 D[2] 1 D[1] 0 D[0] 3.2.64 0x78--Equalizer Read Select Register (eq_add_read) A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 47 decimals. When written, it causes the selected 16-bit location of the equalizer register file to be subsequently loaded into the lowest-order bits of the Access Data Register [access_data_byte[3:0]; 0x7C-0x7F] within two symbol periods. Does not affect the value of the register file location. An address map of the shared register file, as defined by the factory-delivered microcode, is shown below. 7 - 6 - 5 D[5] 4 D[4] 3 D[3] 2 D[2] 1 D[1] 0 D[0] D[5:0] Stored Parameter Decimal 0-7 8-15 16-20 21-25 26 27 28 29 30 31 32 33 34 35-47 Binary 00 0000-00 0111 00 1000-00 1111 01 0000-01 0100 01 0101-01 1001 01 1010 01 1011 01 1100 01 1101 01 1110 01 1111 10 0000 10 0001 10 0010 10 0011-10 1111 FFE Coefficients 0-7 FFE Data Taps 0-7 EP Coefficients 0-4 EP Data Taps 0-4 DAGC Gain - Least-Significant Word DAGC Gain - Most-Significant Word DAGC Output FFE Output DAGC Input FFE Output, Delayed 1 Symbol Period DAGC Error Signal Equalizer Error Signal Slicer Error Signal Reserved N8960DSB 69 3.0 Registers 3.1 Conventions BT8960 Single-Chip 2B1Q Transceiver 3.2.65 0x79--Equalizer Write Select Register (eq_add_write) A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 47 decimals. When written, it causes the lowest-order 16 bits of the Access Data Register [access_data_byte[3:0]; 0x7C- 0x7F] to be subsequently written to the selected equalizer register file location within two symbol periods. Does not affect the value of the access data register. An address map of the shared register file, as defined by the factory-delivered microcode, is shown below. 7 - 6 - 5 D[5] 4 D[4] 3 D[3] 2 D[2] 1 D[1] 0 D[0] 3.2.66 0x7A--Equalizer Microcode Read Select Register (eq_microcode_add_read) A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimals. When written, it causes the selected 32-bit location of the equalizer microprogram store to be subsequently loaded into the Access Data Register [access_data_byte[3:0]; 0x7C-0x7F] within two symbol periods. Does not affect the value of the microprogram store location. 7 - 6 - 5 D[5] 4 D[4] 3 D[3] 2 D[2] 1 D[1] 0 D[0] 3.2.67 0x7B--Equalizer Microcode Write Select Register (eq_microcode_add_write) A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimals. When written, it causes all 32 bits of the Access Data Register [access_data_byte[3:0]; 0x7C-0x7F] to be subsequently written to the selected equalizer microprogram store location within two symbol periods. Does not affect the value of the access data register. Factory-developed equalizer microcode is included with the no-fee licensed HDSL transceiver software available from Rockwell. 7 - 6 - 5 D[5] 4 D[4] 3 D[3] 2 D[2] 1 D[1] 0 D[0] 3.2.68 0x7C-0x7F--Access Data Register (access_data_byte3:0) A 4-byte read/write register stores filter coefficient, equalizer register file, and equalizer microprogram store contents during indirect accesses to these RAM-based locations. Writes to addresses 0x70 through 0x7B, utilize the contents of this shared register as specified in each of the individual register descriptions. 70 N8960DSB 4.0 Electrical & Mechanical Specifications 4.1 Absolute Maximum Ratings Stresses above those listed may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4-1. Absolute Maximum Ratings Symbol VSupply VI TST TVSOL Supply Voltage(1) Input Voltage on any Signal Pin(2) Storage Temperature Vapor-Phase Soldering Temperature (1 minute) Parameter Minimum -0.5 -0.5 -65 Maximum +7 VDD2 + 0.5 +125 +220 Units V V C C Notes: (1). VDD1, VDD2, relative to DGND. VAA relative to AGND. (2). Relative to DGND. N8960DSB 71 4.0 Electrical & Mechanical Specifications 4.2 Recommended Operating Conditions BT8960 Single-Chip 2B1Q Transceiver 4.2 Recommended Operating Conditions Table 4-2. Recommended Operating Conditions Symbol VDD1 VDD2 VAA VIH VIL VIHX VILX CL TA Parameter Digital Core-Logic Supply Voltage Digital I/O-Buffer Supply Voltage Analog Supply Voltage High-Level Input Voltage Low-Level Input Voltage High-Level Input Voltage for XTALI / MCLK Low-Level Input Voltage for XTALI / MCLK Output Capacitive Loading(1) Ambient Operating Temperature(2) Minimum 4.75 4.75 4.75 2.0 -0.3 0.8*VDD2 -0.3 Typical 5.0 5.0 5.0 Maximum 5.25 5.25 5.25 VDD2 + 0.3 +0.8 VDD2 + 0.3 0.2*VDD2 60 Units V V V V V V V pF C -40 +85 Notes: (1). Capacitive loading over which all digital output switching characteristics are guaranteed. (2). Still-air temperature range over which all electrical characteristics and timing requirements/characteristics are guaranteed. 72 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 4.0 Electrical & Mechanical Specifications 4.3 Electrical Characteristics 4.3 Electrical Characteristics Typical characteristics measured at nominal operating conditions: TA = 25 C; VDD/AA = 5.0 V minimum/maximum characteristics guaranteed over extreme operating conditions: min TA max; min VDD/AA max. Table 4-3. Electrical Characteristics Symbol VOH VOLL VOL II IOZ IPR ITOTAL ITOTAL ITOTAL IPD IPD IPD CI COZ Parameter High-Level Output Voltage @ IOH = -400 A Low-Level Output Voltage @ IOL = 6 mA (IRQ and READY) Low-Level Output Voltage @ IOL = 3 mA (All Other Outputs) Input Leakage Current @ VSS2 VI VDD2 High-Impedance Output Leakage Current @ VSS2 VO VDD2 Resistive Pull-Up Current @ VI = VSS2 (TDI and TMS) Total Supply Current @ FQCLK = 208 kHz (N=6)(1) Total Supply Current @ FQCLK = 144 kHz (N=4)(1) Total Supply Current @ FQCLK = 80 kHz (N=2)(1) Total Power-Down Current @ FQCLK = 208 kHz (N=6)(2) Total Power-Down Current @ FQCLK = 144 kHz (N=4)(2) Total Power-Down Current @ FQCLK = 80 kHz (N=2)(2) Input Capacitance High-Impedance Output Capacitance Minimum 2.4 Typical Maximum Units V 0.4 0.4 10 10 -100 133 120 106 TBD TBD TBD 10 10 -800 147 131 117 V V A A A mA mA mA mA mA mA pF pF Notes: (1). ITOTAL = IDD1 + IDD2 + IAA during normal operation. (2). ITOTAL = IDD1 + IDD2 + IAA during power-down operation. N8960DSB 73 4.0 Electrical & Mechanical Specifications 4.4 Clock Timing BT8960 Single-Chip 2B1Q Transceiver 4.4 Clock Timing Table 4-4. External Clock Timing Requirements (MCLK) Symbol 1 2 3 Parameter MCLK Period (TMCLK)(1) MCLK Pulse-Width Low MCLK Pulse-Width High Minimum 75 30 30 Maximum 196 Units ns ns ns Note: (1). If an external clock is applied to XTALI/MCLK, it is referred to as MCLK. Figure 4-1. MCLK Timing Requirements 1 3 2 MCLK Table 4-5. HCLK Switching Characteristics Symbol 4 Parameter HCLK Period (THCLK), hclk_freq[1:0] = `00' or `11' (N=6)(1) HCLK Period (THCLK), hclk_freq[1:0] = `01' (N=2)(1) HCLK Period (THCLK), hclk_freq[1:0] = `10' (N=4)(1) HCLK Pulse-Width High HCLK Pulse-Width Low Minimum TQCLK /64 TQCLK /16 TQCLK /32 THCLK / 2 - 10 THCLK / 2 - 10 Typical TQCLK /64 TQCLK /16 TQCLK /32 THCLK / 2 THCLK / 2 Maximum TQCLK /64 TQCLK /16 TQCLK /32 THCLK / 2 + 10 THCLK / 2 + 10 Units 5 6 7 8 ns ns Notes: (1). The hclk_freq[1:0] control bits are located in the Serial Monitor Source Select Register [addr. 0x01]. 74 N8960DSB BT8960 Single-Chip 2B1Q Transceiver Table 4-6. Symbol Clock (QCLK) Switching Characteristics Symbol 9 10 11 12 13 QCLK Period (TQCLK)(1) QCLK Pulse-Width High QCLK Pulse-Width Low QCLK Hold after HCLK Rising Edge QCLK Delay after HCLK High 4.0 Electrical & Mechanical Specifications 4.4 Clock Timing Parameter Minimum K x THCLK TQCLK / 2 - 20 TQCLK / 2 - 20 -20 Maximum K x THCLK TQCLK / 2 + 20 TQCLK / 2 + 20 Units ns ns 20 Note: (1). K = 16, 32 or 64 according to hclk_freq[1,0]. QCLK can be frequency locked to the incoming data symbol rate. Figure 4-2. Clock Control Timing 4,5,6 7 HCLK 8 13 12 QCLK 11 10 9 N8960DSB 75 4.0 Electrical & Mechanical Specifications 4.5 Channel Unit Interface Timing BT8960 Single-Chip 2B1Q Transceiver 4.5 Channel Unit Interface Timing Table 4-7. Channel Unit Interface Timing Requirements, Parallel Master Mode Symbol 14 15 Parameter TQ[1,0] Setup prior to QCLK Falling Edge TQ[1,0] Hold after QCLK Low Minimum 100 25 Maximum Units ns ns Table 4-8. Channel Unit Interface Switching Characteristics, Parallel Master Mode Symbol 16 17 Parameter RQ[1,0] Hold after QCLK Rising Edge RQ[1,0] Delay after QCLK High Minimum -50 Maximum Units ns 50 ns Figure 4-3. Channel Unit Interface Timing, Parallel Master Mode RQ[1,0] 16 17 QCLK 14 15 TQ[1,0] 76 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 4.0 Electrical & Mechanical Specifications 4.5 Channel Unit Interface Timing Table 4-9. Channel Unit Interface Timing Requirements, Parallel Slave Mode Symbol 18 19 20 21 22 TBCLK, RBCLK Period(1) TBCLK, RBCLK Pulse-Width High TBCLK, RBCLK Pulse-Width Low TQ[1,0] Setup prior to TBCLK Active Edge(2) TQ[1,0] Hold after TBCLK High/Low(2) Parameter Minimum TQCLK TQCLK / 4 TQCLK / 4 25 25 Maximum TQCLK Units ns ns Notes: (1). TBCLK and RBCLK must be frequency locked to QCLK though they may have independent phase relationships to QCLK and to one another. (2). TBCLK polarity (edge sensitivity) is programmable through the CU Interface Modes Register [cu_interface_modes 0x06]. Table 4-10. Channel Unit Interface Switching Characteristics, Parallel Slave Mode Symbol 23 24 Parameter RQ[1,0] Hold after RBCLK Active Edge(1) RQ[1,0] Delay after RBCLK High/Low(1) Minimum 0 Maximum Units ns 100 ns Notes: (1). RBCLK polarity (edge sensitivity) is programmable through the CU Interface Modes Register [cu_interface_modes; 0x06]. Figure 4-4. Channel Unit Interface Timing, Parallel Slave Mode 18 RBCLK 19 23 20 24 RQ[1:0] 18 TBCLK 19 21 22 20 TQ[1:0] Note: TBCLK and RBCLK polarities are programmable through the CU Interface Modes register. The figure depicts both clocks programmed to falling-edge active. N8960DSB 77 4.0 Electrical & Mechanical Specifications 4.5 Channel Unit Interface Timing BT8960 Single-Chip 2B1Q Transceiver Table 4-11. Channel Unit Interface Timing Requirements, Serial Mode Symbol 25 26 Parameter TDAT Setup prior to BCLK Falling Edge TDAT Hold after BCLK Low Minimum 100 25 Maximum Units ns ns Table 4-12. Channel Unit Interface Switching Characteristics, Serial Mode Symbol 27 28 29 30 31 32 33 BCLK Period BCLK Pulse-Width High BCLK Pulse-Width Low BCLK Hold after HCLK Rising Edge BCLK Delay after HCLK High RDAT, QCLK Hold after BCLK Rising Edge RDAT, QCLK Delay after BCLK High -50 50 Parameter Minimum TQCLK / 2 TQCLK / 4 - 20 TQCLK / 4 - 20 0 Maximum TQCLK / 2 TQCLK / 4 + 20 TQCLK / 4 + 20 Units ns ns ns 50 ns ns ns Figure 4-5. Channel Unit Interface Timing, Serial Mode HCLK 31 30 BCLK 29 33 32 QCLK 28 27 RDAT 25 26 TDAT 78 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 4.0 Electrical & Mechanical Specifications 4.6 Microcomputer Interface Timing 4.6 Microcomputer Interface Timing Table 4-13. Microcomputer Interface Timing Requirements Symbol 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ALE Pulse-Width High Address Setup prior to ALE Falling Edge(1) Address Hold after ALE Low(1) ALE low prior to Write Strobe Falling Edge(2) ALE low prior to Read Strobe Falling Edge(3,4) Write Strobe Pulse-Width Low(2,5) Read Strobe Pulse-Width Low(3,5) Data In Setup prior to Write Strobe Rising Edge(2) Data In Hold after Write Strobe High(2) R/W Setup prior to Read/Write Strobe Falling Edge R/W Hold after Read/Write Strobe High ALE Falling Edge after Write Strobe High ALE Falling Edge after Read Strobe High RST Pulse-Width Low Write Strobe Rising Edge after READY low Parameter Minimum 30 12 5 20 -27 2*Tmclk +25 2*Tmclk +25 30 5 10 10 20 20 50 0 Maximum Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: (1). Address is defined as AD[7:0] when MUXED = 1, and ADDR[7:0] when MUXED = 0. (2). In Intel mode, Write Strobe is defined as WR and CS asserted. In Motorola mode, it is defined as DS and CS asserted when R/W is low. (3). In Intel mode, Read Strobe is defined as RD and CS asserted. In Motorola mode, it is defined as DS and CS asserted when R/W is high. (4). Parameter 38 is -27 ns only if separate address and data busses are used (i.e., muxed = 0). If muxed = 1, then parameter 38 is 20 ns. (5). The timing listed is for the synchronous mode of the MCI. It can also be set to synchronous mode by setting bit 0 of the reserved2 register (address 0x0F) to a 1. In this case the minimum timing changes to 40 us for symbol 39, and 50 us for symbols 40 and 50. Synchronous mode is preferred because it reduces internal switching noise, however no significant performance degradation has been measured as a result of using the asynchronous mode. N8960DSB 79 4.0 Electrical & Mechanical Specifications 4.6 Microcomputer Interface Timing BT8960 Single-Chip 2B1Q Transceiver Table 4-14. Microcomputer Interface Switching Characteristics Symbol 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Parameter Data Out Enable (Low Z) after Read Strobe Falling Edge(1) Data Out Valid after Read Strobe Low(1,7) Data Out Hold after Read Strobe Rising Edge(1) Data Out Disable (High Z) after Read Strobe High(1) IRQ Hold after Write Strobe Rising Edge(2,3) IRQ Delay after Write Strobe High(2,3) Internal Register Delay after Write Strobe High(3,4) Internal RAM Delay after Write Strobe High(3,5) Access Data Register Delay after Write Strobe High(3,6) READY Falling Edge after Write Strobe Low(3) READY Rising Edge after Write Strobe High(3) READY Falling Edge after Read Strobe Low(1) READY Rising Edge after Read Strobe High(1) Data Out Valid after READY low Minimum 2 Maximum Units ns 2* Tmclk +25 2 25 5 Tqclk / 32 + 20 Tqclk / 32 2*Tqclk 2* Tqclk 0 0 0 0 2*Tmclk +25 50 2*Tmclk +25 50 10 ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: (1). Read Strobe is defined as RD and CS asserted in Intel mode, and DS and CS asserted when R/W is high in Motorola mode. (2). When writing an interrupt mask or status register. (3). Write Strobe is defined as WR and CS asserted in Intel mode, and DS and CS asserted when R/W is low in Motorola mode. (4). Writes to internal registers are synchronized to an internal 64-times symbol-rate clock. Data is available for reading after the specified time. This parameter may extend the overall read access time from internal register locations under high bus speed/low symbol rate conditions. (5). When performing an indirect write to RAM-based locations using a write select register [odd addresses: 0x71-0x7B] and the Access Data Register. Subsequent writes to any read/write select register or the Access Data Register, as initiated by a Write Strobe falling edge, is prohibited for the specified time. This parameter will extend the overall write access time to RAM-based locations under normal bus speed/symbol rate conditions. (6). When performing an indirect read from RAM-based locations using a read select register [even addresses: 0x70-0x7A] and the Access Data Register. Subsequent writes to any read/write select register, as initiated by a Write Strobe falling edge, is prohibited for the specified time. Data is available for reading from the Access Data Register after the specified time. This parameter will extend the overall read access time from RAM-based locations under normal bus speed/symbol rate conditions. Direct writes to the Access Data Register are as specified for internal registers. (7). The timing listed is for the synchronous mode of the MCI. It can also be set to synchronous mode by setting bit 0 of the reserved2 register (address 0x0F) to a 1. In this case the minimum timing changes to 40 us for symbol 39, and 50 us for symbols 40 and 50. Synchronous mode is preferred because it reduces internal switching noise, however no significant performance degradation has been measured as a result of using the asynchronous mode. 80 N8960DSB BT8960 Single-Chip 2B1Q Transceiver Figure 4-6. MCI Write Timing, Intel Mode (MOTEL = 0) AD[7:0] or ADDR[7:0] 4.0 Electrical & Mechanical Specifications 4.6 Microcomputer Interface Timing Address 35 36 Data (Input) 41 42 Write Strobe 37 39 34 48 ALE 58 READY 59 45 Figure 4-7. MCI Write Timing, Motorola Mode (MOTEL = 1) AD[7:0] or ADDR[7:0] Address 35 36 Data (Input) 41 42 Write Strobe 37 39 48 R/W 43 34 58 ALE 59 READY 44 45 N8960DSB 81 4.0 Electrical & Mechanical Specifications 4.6 Microcomputer Interface Timing BT8960 Single-Chip 2B1Q Transceiver Figure 4-8. MCI Read Timing, Intel Mode (MOTEL = 0) AD[7:0] or ADDR[7:0] Address 35 36 38 49 50 62 Data (Output) 51 52 Read Strobe 40 34 46 ALE 61 READY 60 Figure 4-9. MCI Read Timing, Motorola Mode (MOTEL = 1) AD[7:0] or ADDR[7:0] Address 35 36 38 49 50 62 Data (Output) 51 52 Read Strobe 40 43 44 R/W 34 46 ALE 60 READY 61 82 N8960DSB BT8960 Single-Chip 2B1Q Transceiver Figure 4-10. Internal Write Timing Write Strobe 4.0 Electrical & Mechanical Specifications 4.6 Microcomputer Interface Timing 54 53 IRQ 55 Internal Register 56 Internal RAM 57 Access Data Register N8960DSB 83 4.0 Electrical & Mechanical Specifications 4.6 Microcomputer Interface Timing BT8960 Single-Chip 2B1Q Transceiver 4.6.1 Test and Diagnostic Interface Timing Table 4-15. Test and Diagnostic Interface Timing Requirements Symbol 56 57 58 59 TCK Pulse-Width High TCK Pulse-Width Low TMS, TDI Setup prior to TCK Rising Edge(1) TMS, TDI Hold after TCK High(1) Parameter Minimum 80 80 20 20 Maximum Units ns ns ns ns Note: (1). Also applies to functional inputs for SAMPLE/PRELOAD and EXTEST instructions. Table 4-16. Test and Diagnostic Interface Switching Characteristics Symbol 60 61 62 63 64 65 TDO Hold after TCK Falling Edge(1) TDO Delay after TCK Low(1) TDO Enable (Low Z) after TCK Falling Edge(1) TDO Disable (High Z) after TCK Low(1) SMON Hold after HCLK Rising Edge(2) SMON Delay after HCLK High(2) 0 50 2 25 Parameter Minimum 0 Maximum Units ns 50 ns ns ns ns ns Notes: (1). Also applies to functional outputs for the EXTEST instruction. (2). HCLK must be programmed to operate at 16 times the symbol rate (16 x FQCLK). 84 N8960DSB BT8960 Single-Chip 2B1Q Transceiver Figure 4-11. JTAG Interface Timing 4.0 Electrical & Mechanical Specifications 4.6 Microcomputer Interface Timing TDO 62 56 TCK 58 59 57 60 61 63 TDI TMS Figure 4-12. SMON Timing HCLK 65 64 SMON N8960DSB 85 4.0 Electrical & Mechanical Specifications 4.6 Microcomputer Interface Timing BT8960 Single-Chip 2B1Q Transceiver 4.6.2 Analog Specifications Table 4-17. Receiver Analog Requirements and Specifications Parameter Input Signals Input Voltage Range Input Resistance Common Mode Voltage Variable Gain Amplifier (VGA) Gain Step Gain Error Analog-to-Digital Converter Output Symbol Rate (FQCLK) Differential Voltage Range (Full Scale Input, FS)(1) Timing Recovery PLL Pull-In Range QCLK frequency (Data Rate/2) (VRXP-VRXN)--(VRXBP-VRXBN) 75 5.4 64 6.0 210 6.6 kHz VP ppm Comments RXP, RXN, RXBP, and RXBN Balanced Differential DC to 1 MHz VCOMI Six gains from 0 dB to +15 dB Min Typ Max Units -4.5 28 0.4*VAA +4.5 V k 2.55 3.0 3.42 10 dB % Note: (1). Corresponds to the voltages that will produce a full scale reading from the ADC when the VGA gain equals O dB. Input voltage range is reduced proportionally as VGA gain is increased. 86 N8960DSB BT8960 Single-Chip 2B1Q Transceiver Table 4-18. Transmitter Analog Requirements and Specifications Parameter Transmit Symbol Rate (fqclk) Pulse Template(1, 2,3) Average Power(1, 2,4) Gain Adjustment Step 4.0 Electrical & Mechanical Specifications 4.6 Microcomputer Interface Timing Comments QCLK Frequency (Data Rate/2) See Figure 4-13, RL = 135 DC to 2xFQCLK, RL = 135 , 0dB gain setting Controlled by Transmit Gain Register [0x29]. Seven steps above and eight steps below 0 dB. Min 75 Typ Max 210 Units kHz 13.4 0.17 0.20 14.0 0.24 dBm dB Output Referred Offset Voltage Output Current Common-Mode Voltage Output Impedance(1) Linearity Harmonic Distortion VCOMO DC to 1 MHz At Output Symbol Peak 3 kHz, 3.4 V Peak Sine Wave Output, RL =0 0.01 -70 125 VAA/2 25 mV mA V 2 W %FSR(5) dB Notes: (1). Guaranteed by design and characterization. (2). See 4-14 of the Test Conditions section of this datasheet for test circuit. (3). Measured after the transmitter is calibrated by writing the value in the Transmitter Calibration Register [tx_calibrate; 0x28] to the Transmitter Gain Register [tx_gain; 0x29]. (4). Measured with a pseudo-random code sequence of pulses. (5). FSR is Full Scale Range. N8960DSB 87 4.0 Electrical & Mechanical Specifications 4.6 Microcomputer Interface Timing BT8960 Single-Chip 2B1Q Transceiver Figure 4-13. Transmitted Pulse Template -0.4T B = 1.07 C = 1.00 D = 0.93 T = 1/FQCLK 0.4T 1.25T A = 0.01 F = -0.01 -1.2T -0.6T E = 0.03 H = -0.05 A = 0.01 F = -0.01 14T 50T 0.5T G = -0.16 Table 4-19. Transmitted Pulse Template Normalized Level +3 A B C D E F G H 0.01 1.07 1.00 0.93 0.03 -0.01 -0.16 -0.05 0.0264 2.8248 2.6400 2.4552 0.0792 -0.0264 -0.4224 -0.1320 Quaternary Symbols +1 0.0088 0.9416 0.8800 0.8184 0.0264 -0.0088 -0.1408 -0.0440 -1 -0.0088 -0.9416 -0.8800 -0.8184 -0.0264 0.0088 0.1408 0.0440 -3 -0.0264 -2.8248 -2.6400 -2.4552 -0.0792 0.0264 0.4224 0.1320 88 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 4.0 Electrical & Mechanical Specifications 4.6 Microcomputer Interface Timing 4.6.3 Test Conditions Figure 4-14. Transmitter Test Circuit 3.01 k 1 k TXPSP (67) C8 1 k TXPSN (68) 1 k TXLDIN (70) 1 k TXLDIP (69) + Line Driver + - TXP (71) TXN (74) 3.01 k 16.2 16.2 1:2 + Line Transformer - + RL _ Note: See Table 4-20 for C8 and transformer values. N8960DSB 89 4.0 Electrical & Mechanical Specifications 4.6 Microcomputer Interface Timing BT8960 Single-Chip 2B1Q Transceiver Table 4-20. Transmitter Test Circuit Component Values Data Rate Component 288 kbps C8 L (Primary Inductance - Line Side) 1.8 nF 5.0 mH 416 kbps 4.7 nF 3.5 mH Figure 4-15. Standard Output Load (Totem Pole and Three-State Outputs) IOL From BT8960 CL 1.5 V IOH Figure 4-16. Open-Drain Output Load (IRQ) IOD From BT8960 CL VDD2 90 N8960DSB BT8960 Single-Chip 2B1Q Transceiver 4.0 Electrical & Mechanical Specifications 4.7 Timing Measurements 4.7 Timing Measurements The input waveforms are shown in Figure 4-17. Output waveforms are displayed in Figures 4-18 and 4-19. Figure 4-17. Input Waveforms for Timing Tests 3V 2.0 V 0.8 V 0V Input high Input Low Input Low Input high Figure 4-18. Output Waveforms for Timing Tests VDD 2.4 V 0.4 V 0 V Output high Output Low Output Low Output high N8960DSB 91 4.0 Electrical & Mechanical Specifications 4.8 Mechanical Specifications BT8960 Single-Chip 2B1Q Transceiver Figure 4-19. Output Waveforms for Three-state Enable and Disable Tests VOH - 0.2 V 1.7 V 1.5 V 1.3 V VOL + 0.2 V Output Disabled Output Enabled Output Disabled 4.8 Mechanical Specifications 92 N8960DSB BT8960 Single-Chip 2B1Q Transceiver Figure 4-20. 100-Pin Plastic Quad Flat Pack 4.0 Electrical & Mechanical Specifications 4.8 Mechanical Specifications N8960DSB 93 Please mail or fax this form to: Rockwell Semiconductor Systems Manager, Technical Publications Dept. (619) 597-4338 READER RESPONSE PAGE e welcome your evaluation of this publication. Your comments and suggestions will help us make improvements to all current and future documents. Please rate the following characteristics of the publication you received: W 11. In what format(s) would you prefer to receive future documents? (Check all that apply.) t Printed books t Internet/PDF delivery t CD-ROM t Other: _____________________________ 12. How would you rank the importance of the following publication features? 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